Securing Emerging Nonvolatile Main Memory With Fast and Energy-Efficient AES In-Memory Implementation

IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption

“…High throughput AES encryption/decryption is extremely desirable in many applications (e.g., virtual private networks, electronic financial transactions, etc.). As demonstrated in previous work (e.g., [2]- [7]), hardware accelerators designed for AES encryption/decryption can achieve high throughput while enabling area-efficient design alternatives for resource-constrained environments such as edge computing. AES hardware accelerators are usually application-specific integrated circuits (ASICs) or field-programmable gate array (FPGA)-based co-processors that implement the steps for the AES algorithm, i.e., AddRoundKey, SubBytes/InvSubBytes, ShiftRows, and MixColumns/InvMixColumns.…”

“…Numerous research efforts have been devoted to developing FPGA or ASIC-based hardware to accelerate AES (e.g., [2]- [7], [19], [20]). That said, designing a hardware accelerator for AES that can provide high throughput without large overheads in terms of area and power consumption can be a challenging task.…”

“…To address the memory bottleneck of AES, in-memory computing (IMC) architectures (i.e., with modified memory cells or peripherals) may be designed to perform operations commonly found in AES-based encryption/decryption (e.g., bit shifts, byte permutations and XOR). IMC-based architectures operate on memory words without the need for data transfers to a processing unit (e.g., [6], [7]). Despite the potential for reduced data traffic, work in [6], [7] must make tradeoffs between area/power efficiency and parallelism.…”

“…IMC-based architectures operate on memory words without the need for data transfers to a processing unit (e.g., [6], [7]). Despite the potential for reduced data traffic, work in [6], [7] must make tradeoffs between area/power efficiency and parallelism. To this end, accelerators based on lookup table (LUT) and precomputed operations (e.g., [2], [3]) have demonstrated high levels of parallelism and throughput.…”

“…We have performed detailed circuit-level, simulation-based evaluations of our proposed IMCRYPTO architecture. We consider figures of merit such as delay, area, power, throughput, area-delay-power product (ADPP), and throughput per area and compare them with state-of-the-art ASIC and IMC-based accelerators for AES encryption [4]- [7]. Results indicate minimum (maximum) throughput per area improvements of 3.3× (223.1×) and minimum (maximum) ADPP improvements of 1.2× (6,238.3×) for CMOS-based IMCRYPTO when compared to ASIC and IMC accelerators for AES-128 encryption of a 1MB plaintext.…”