Securing IEEE 1687-2014 Standard Instrumentation Access by LFSR Key

Liu, Hejia; Agrawal, Vishwani D.

doi:10.1109/ats.2015.23

Cited by 30 publications

(4 citation statements)

References 8 publications

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“…In fact, the authors proposed a parallel IJTAG structure with increased bandwidth and showed that using LSIBs instead of SIBs, the same security level is granted. H. Liu and V. Agrawal [33] proposed a different kind of LSIB that relies on a Secure LFSR (SLFSR) integrated in the scan network. The SLFSR is placed downstream the LSIB that must be protected.…”

Section: ) Locking Sibmentioning

confidence: 99%

“…The techniques based on LSIBs presented in [20] and [33] rely on a secret password established at design time and hardwired inside the logic of the LSIB. Moreover, the solution [33] also relies on an LFSR whose polynomial is established at design time. For this reason, any leak of this information undermines the security of all the samples that share the same design.…”

Section: ) Locking Sibmentioning

confidence: 99%

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A Survey on Security Threats and Countermeasures in IEEE Test Standards

et al. 2019

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The growth in complexity of Integrated Circuits (IC) is supported, amongst other factors, by the development of standardized test infrastructures. The feasibility of both end-ofmanufacturing and in-field tests heavily depends on the presence of these infrastructures that give detailed access to the IC. The standard test infrastructures are referred as IEEE Std. 1149.1 (JTAG), IEEE Std. 1500 and IEEE Std. 1687 (IJTAG). The security issues arising from the presence of these infrastructures have been fully exposed in the last two decades. This led to the publication of several practical attacks showing how a non-protected test infrastructure can end into the jeopardizing of the entire system. As a consequence, many countermeasures have been proposed. In this survey, we provide: (i) a taxonomy of the attacks that can be performed exploiting the standard test infrastructures; (ii) a taxonomy of countermeasures inspired by the kind of security primitives that are granted in each case.

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Section: ) Locking Sibmentioning

confidence: 99%

Section: ) Locking Sibmentioning

confidence: 99%

A Survey on Security Threats and Countermeasures in IEEE Test Standards

et al. 2019

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“…IEEE P1687 标准 [1] 也被称为内部联合测试行动组(internal joint test action group, IJTAG), 使用段插入位(segment insert bit, SIB)构建可重构扫描网络, 通过向 SIB 移入配置数据改变扫描链. 虽然在可重构扫描网络中可以灵活地配置扫描路径, 但是也存在着一些安全问题 [2][3] [4][5][6][7][8][9][10][11][12] ; 另一类是防止恶意仪器对传输数据的窜改和嗅探攻击 [13][14][15][16] . 文献 [4][5] 通过使用多个分布式密钥位增大未经授权用户对重要仪器访问的难度.…”

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“…文献 [4][5] 通过使用多个分布式密钥位增大未经授权用户对重要仪器访问的难度. 文献 [6][7] [4][5][6][7][8][9][10][11][12] , 能使 IJTAG 网络免受恶意仪器对传输数据的嗅探或窜改 [13][14][15][16] Step1.…”

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Lock Isolation Security Architecture for Reconfigurable Scanning Networks

Liu

Wang

Ren

2021

J Comput-Aided Design Comput Graphics

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To protect the reconfigurable scanning network from the influence of unauthorized access, tampering of transmitted data by malicious instruments and sniffing, a lock isolation security structure is proposed. Firstly, the presented structure divides the instruments without security threat to each other into one group, and the groups can be accessed one by one via the isolated signals, which can prevent malicious instruments tampering and sniffing transmitted data. Secondly, the key instruments are protected by the lock segment insertion bit. The lock segment insertion bit can only be opened when multiple key values at specific positions are set to specific values (0, 1 sequence), which can increase the difficulty of unauthorized access. Besides, to reduce the hardware overhead, and the difficulty of place and route caused by excessive instrument groups, instrument grouping algorithm is proposed. The proposed algorithm firstly constructs an undirected graph based on the security relationship among instruments. Then the maximal independent sets of the undirected are obtained. In this way, the number of instrument groups is reduced greatly. Compared to other similar methodologies, the experimental results conducted on ITC 02 benchmark circuits show that the time consumption for opening the locking segment insertion bit of the proposed security structure increased by 7 times, and the average percentage reduction of area, power consumption and wire length is 3.81%, 9.02% and 4.55%, respectively.

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