Securing IoT/IIoT from Software Attacks Targeting Hardware Vulnerabilities

Polychronou, Nikolaos Foivos; Thevenon, Pierre-Henri; Puys, Maxime; Beroulle, Vincent

doi:10.1109/newcas50681.2021.9462776

Cited by 4 publications

(3 citation statements)

References 7 publications

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“…We benefit from HPCs to measure the stress that malicious applications induce in the hardware components of the microprocessor. We developed a testbench [12] that allows experimenting and evaluating different side effects. In this case, the side effects represent the differences in the behavior of HPCs in the presence or not of a malicious vector.…”

Section: Methodsmentioning

confidence: 99%

“…In this case, the side effects represent the differences in the behavior of HPCs in the presence or not of a malicious vector. In [12], we presented the testbench which allows us to measure the efficiency of State Of The Art (SOTA) solutions in different architectures. We studied simple thresholdbased implementations targeting to detect only CacheSCA and Rowhammer.…”

Section: Methodsmentioning

confidence: 99%

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MaDMAN: Detection of Software Attacks Targeting Hardware Vulnerabilities

Polychronou

Thevenon

Puys

et al. 2021

2021 24th Euromicro Conference on Digital System Design (DSD)

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The increasing complexity of modern microprocessors created new attack areas. Attackers exploit these areas using Software Attacks Targeting Hardware Vulnerabilities (SATHV) such as Cache Side-Channel, Spectre, and Rowhammer attacks. These attacks target the microarchitecture to extract privileged information. As their target is the hardware, antivirus programs cannot detect them. But, they modify the normal behavior of the microarchitecture. Modern systems are equipped with hardware performance counters (HPCs), which measure events related to hardware components. Designers can take advantage of these counters to monitor and protect the system. In the literature, there exist many solutions that use HPCs to detect SATHV. But, due to the limited number of counters, proposed solutions only protect the microprocessor against a limited set of SATHV. In contrast, we propose MaDMAN, a Malware Detector, which gathers information from HPCs to detect a large set of SATHV. MaDMAN uses a Logistic Regression classifier. In our threat model, we include Cache Side-Channel, Rowhammer, and Spectre SATHV. Our detection mechanism succeeds to detect these attacks with 98.96% accuracy, 96.3% F-score, and 0% false positive rate. In addition, MaDMAN works in noisy environments and can detect successfully evasive malware.

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Section: Methodsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

MaDMAN: Detection of Software Attacks Targeting Hardware Vulnerabilities

Polychronou

Thevenon

Puys

et al. 2021

2021 24th Euromicro Conference on Digital System Design (DSD)

Self Cite

View full text Add to dashboard Cite

show abstract

“…Side-channel attacks use information, such as sound, power, and time, leaked by a system (especially the cryptosystem) to crack the system (key) [6,7]. Cache attacks are side-channel attacks that pose a significant threat to IoT devices [8,9]; they mainly exploit the inherent vulnerability of modern processors. They differ entirely from pure software attacks.…”

Section: Introductionmentioning

confidence: 99%

Evaluation on the Impact of Cache Parameter Selection in Access-Driven Cache Attacks

Guo

Yan

et al. 2022

Electronics

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Cache attacks exploit the hardware vulnerabilities inherent to modern processors and pose a new threat to Internet of Things (IoT) devices. Intuitively, different cache parameter configurations directly impact the attack effectiveness, but the current research on this issue is not systematic or comprehensive enough. This paper’s primary focus is to evaluate how different cache parameter configurations affect access-driven attacks. We build a flexible and configurable simulation verification environment based on the Chipyard framework. To reduce the interference of other factors, we established a baseline for each category of parameter evaluation. We propose a novel evaluation model, called Key Score Scissors Differential (KSSD), for evaluating common private and shared cache parameters under the local and cross-core attack models, respectively; among these are private cache replacement policy, private cache capacity, cache line size, private cache associativity, shared cache capacity, and shared cache associativity. Ours is the first evaluation of the shared cache under a cross-core attack model. As a result of the evaluation, the quantitative metrics can provide a reliable indication of information leakage level under the current cache configuration, which is helpful for attackers, defenders, and evaluators. Furthermore, we provide detailed explanations and discussions of inconsistent findings by comparing our results with the existing literature.

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AES-ECC and Blockchain in Optimizing the Security of Communication-Rich IoT

Souare,

Keita

2024

Lecture Notes in Networks and Systems

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Securing IoT/IIoT from Software Attacks Targeting Hardware Vulnerabilities

Cited by 4 publications

References 7 publications

MaDMAN: Detection of Software Attacks Targeting Hardware Vulnerabilities

MaDMAN: Detection of Software Attacks Targeting Hardware Vulnerabilities

Evaluation on the Impact of Cache Parameter Selection in Access-Driven Cache Attacks

AES-ECC and Blockchain in Optimizing the Security of Communication-Rich IoT

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