Security analysis of logic obfuscation

Rajendran, Jeyavijayan; Pino, Youngok; Sinanoglu, Ozgur; Karri, Ramesh

doi:10.1145/2228360.2228377

Cited by 419 publications

(222 citation statements)

References 4 publications

Supporting

Mentioning

221

Contrasting

Order By: Relevance

“…The aforementioned techniques are vulnerable to most serious reverse engineering attacks, such as sensitization [5] and Boolean Satisfiability (SAT) based attacks [23]. In general, sensitization attacks use automatic test pattern generation (ATPG) tools to propagate the key-bits to the primary outputs of the encrypted design, while SAT attacks [23] can decrypt the locked circuit and reveal its secret key.…”

Section: Prior Workmentioning

confidence: 99%

“…It is worth noting that the two reversed engineering attacks (propagated/isolated secret key [5] and SAT [23] attacks) assume that an attacker can get a functional IC from the market and obtain the encrypted chip by either IC design or reverse engineering in an untrusted foundry [5,23,36]. Therefore, an adversary can have access to the primary input-output pairs and can also reveal the structure of the circuit.…”

Section: Sat Based Attackmentioning

confidence: 99%

“…In general, the value of the secret key-bits can be propagated to the primary outputs of the locked circuit via supplying certain input patterns and/or muting some other key-bits unless there is a relationship between the inserted key-gates or the insertion is not done randomly through the original design [5]. This happens due to the fact that each inserted key-gate is either an XOR or an XNOR gate.…”

Section: Sensitization Of the Secret Key-bits Based Attackmentioning

confidence: 99%

“…For example, the value of a key-bit will be revealed on a primary output-bit if the second input value of the inserted XOR gate (coming from the internal net of the encrypted netlist) is zero, which can be achieved by a supplying special input pattern. Rajendran et al [5] proposed a technique, namely Smart logic Obfuscation (SO), to prohibit sensitization attack via maximizing the interference graph among the injected key-gates, where the attacker needs many years to break a locked design that has a sufficient number of key-bits. In our proposed encryption-based polymorphic gates, the attacker may sensitize a path from the output of a polymorphic gate to an output on the working device, and, therefore, the logic function can be determined by applying different patterns to the polymorphic gate's input (using ATPG).…”

Section: Sensitization Of the Secret Key-bits Based Attackmentioning

confidence: 99%

“…The required performance overhead for logic encryption purposes can exceed 25% when the number of inserted key-gates (XOR/XNOR) is about 5% of the total number of gates in the combinational International Symposium on Circuits and Systems (ISCAS)-85 benchmark [5]. In order to address this issue, we propose a technique based on the new characteristic of emerging technology for IP protection and hardware attack prevention.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Logic Locking Using Hybrid CMOS and Emerging SiNW FETs

Alasad

Yuan

2017

Electronics

View full text Add to dashboard Cite

Abstract:The outsourcing of integrated circuit (IC) fabrication services to overseas manufacturing foundry has raised security and privacy concerns with regard to intellectual property (IP) protection as well as the integrity maintenance of the fabricated chips. One way to protect ICs from malicious attacks is to encrypt and obfuscate the IP design by incorporating additional key gates, namely logic encryption or logic locking. The state-of-the-art logic encryption techniques certainly incur considerable performance overhead upon the genuine IP design. The focus of this paper is to leverage the unique property of emerging transistor technology on reducing the performance overhead as well as preserving the robustness of logic locking technique. We design the polymorphic logic gate using silicon nanowire field effect transistors (SiNW FETs) to replace the conventional Exclusive-OR (XOR)-based logic cone. We then evaluate the proposed technique based on security metric and performance overhead.

show abstract

Section: Prior Workmentioning

confidence: 99%

Section: Sat Based Attackmentioning

confidence: 99%

Section: Sensitization Of the Secret Key-bits Based Attackmentioning

confidence: 99%

Section: Sensitization Of the Secret Key-bits Based Attackmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Logic Locking Using Hybrid CMOS and Emerging SiNW FETs

Alasad

Yuan

2017

Electronics

View full text Add to dashboard Cite

show abstract

Hardware and Information Security Primitives Based on 2D Materials and Devices

Wali

Das

2023

Advanced Materials

View full text Add to dashboard Cite

Hardware security is a major concern for the entire semiconductor ecosystem that accounts for billions of dollars in annual losses. Similarly, information security is a critical need for the rapidly proliferating edge devices that continuously collect and communicate a massive volume of data. While silicon‐based complementary metal‐oxide‐semiconductor technology offers security solutions, these are largely inadequate, inefficient, and often inconclusive, as well as resource intensive in time, energy, and cost, leading to tremendous room for innovation in this field. Furthermore, silicon‐based security primitives have shown vulnerability to machine learning (ML) attacks. In recent years, 2D materials such as graphene and transition metal dichalcogenides have been intensely explored to mitigate these security challenges. In this review, 2D‐materials‐based hardware security solutions such as camouflaging, true random number generation, watermarking, anticounterfeiting, physically unclonable functions, and logic locking of integrated circuits (ICs) are summarized with accompanying discussion on their reliability and resilience to ML attacks. In addition, the role of native defects in 2D materials in developing high entropy hardware security primitives is also examined. Finally, the existing challenges for 2D materials, which must be overcome for large‐scale deployment of 2D ICs to meet the security needs of the semiconductor industry, are discussed.

show abstract

Hardware obfuscation of AES IP core using combinational hardware Trojan circuit for secure data transmission in IoT applications

Chhabra

Lata

2022

Concurrency and Computation

View full text Add to dashboard Cite

In semiconductor industry, reusability-based System-on-Chip architecture using hardware intellectual property (IP) cores play a prominent role in Internet-of-Things (IoT) applications for secure data transmission. The advent of IoT makes it possible for physical things to transmit, process, compute, and receive data over internet. But, it also introduces in-device communication security vulnerabilities. Advanced Encryption Standard (AES) IP has been used to address security vulnerabilities in IoT. It is an efficient and high-performance crypto algorithm used in IoT devices for secure and fast data encryption. However, due to rise of many attacks, the security of AES IP is also under threat. Hardware obfuscation is one such prominent countermeasure that mitigates hardware attacks such as tampering, reverse engineering, and malicious alteration. This article presents secure AES IP mechanism using the potential technique of obfuscation inspired by the concept of combinational hardware Trojan. Experimental results show that the proposed technique is resilient against reverse-engineering, malicious alteration, Boolean satisfiability attack, and key-sensitizing attacks. The confusion and diffusion features of obfuscated AES IP are higher in terms of Hamming distance, avalanche effect, and balance rate. The proposed technique is implemented in Basys-3 FPGAs within 5% of power and area overhead while maintaining high throughput.

show abstract

Security analysis of logic obfuscation

Cited by 419 publications

References 4 publications

Logic Locking Using Hybrid CMOS and Emerging SiNW FETs

Logic Locking Using Hybrid CMOS and Emerging SiNW FETs

Hardware and Information Security Primitives Based on 2D Materials and Devices

Hardware obfuscation of AES IP core using combinational hardware Trojan circuit for secure data transmission in IoT applications

Contact Info

Product

Resources

About