Security Threats and Countermeasures in Three-Dimensional Integrated Circuits

Dofe, Jaya; Gu, Peng; Stow, Dylan; Yu, Qiaoyan; Kursun, Eren; Xie, Yuan

doi:10.1145/3060403.3060500

Cited by 21 publications

(14 citation statements)

References 27 publications

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“…Also, various studies are hinting at 3D integration for SM, but most have limitations or cover different scenarios. For example, Dofe et al [20] remain on the conceptional level, or Xie et al [21] and Imeson et al [10] consider 2.5D integration where only wires are hidden from the untrusted foundry. We summarize the prior art on 3D SM in Table 1, along with that for 3D LC.…”

Section: Split Manufacturingmentioning

confidence: 99%

A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

Patnaik

Ashraf²,

Sinanoglu³

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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Split manufacturing (SM) and layout camouflaging (LC) are two promising techniques to obscure integrated circuits (ICs) from malicious entities during and after manufacturing. While both techniques enable protecting the intellectual property (IP) of ICs, SM can further mitigate the insertion of hardware Trojans (HTs). In this paper, we strive for the "best of both worlds," that is we seek to combine the individual strengths of SM and LC. By jointly extending SM and LC techniques toward 3D integration, an up-and-coming paradigm based on stacking and interconnecting of multiple chips, we establish a modern approach to hardware security. Toward that end, we develop a security-driven CAD and manufacturing flow for 3D ICs in two variations, one for IP protection and one for HT prevention. Essential concepts of that flow are (i) "3D splitting" of the netlist to protect, (ii) obfuscation of the vertical interconnects (i.e., the wiring between stacked chips), and (iii) for HT prevention, a security-driven synthesis stage. We conduct comprehensive experiments on DRC-clean layouts of multi-million-gate DARPA and OpenCores designs (and others). Strengthened by extensive security analysis for both IP protection and HT prevention, we argue that entering the third dimension is eminent for effective and efficient hardware security.

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Section: Split Manufacturingmentioning

confidence: 99%

A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

Patnaik

Ashraf²,

Sinanoglu³

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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“…2.5D and 3D integration is a substantial contribution to a possible security increase in IC fabrication. These chip composition techniques are emerging especially in relation with split fabrication processes that should assure the genuineness of IC production in offshore foundries [1][2][3][4][5][6]. Solving supply chain issues is not an aim of our work, and so we will refer readers to the above-mentioned papers for more information on that subject.…”

Section: Complex Integration and Camouflagingmentioning

confidence: 99%

“…Recently, we have seen many papers covering split manufacturing process that allows building reliable and trustworthy devices, at least from the producers' perspective [1][2][3][4][5][6]. In this paper we would like to propose possible techniques for hindering attempts on gaining knowledge from physical examination of chips.…”

Section: Introductionmentioning

confidence: 99%

Improving the Physical Security of Microchip

Malčík¹,

Drahanský²

2019

IJSIA

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Nowadays, microchips are virtually everywhere, from simple home devices to confidential military equipment. We must not forget the medical systems that have a great impact on our quality of life as well. As can be seen, the importance of these tiny integrated circuits is immense. Preserving the reliability of these devices and the confidentiality of data these devices are processing is absolutely substantial. The integrated circuit (IC) industry has been rapidly evolving in recent decades and employing ICs is becoming normal and inevitable in nearly all aspects of our lives. The initial IC evolution era paid attention primarily to the technological evolution itself. Aspects like security were always one step back due to the fallacious feeling of the inherent security of these very tiny components. After realizing that the opposite is true, we have to focus on securing the critical devices against tampering, information theft, counterfeiting, etc. In scope of this paper, it means especially hindering of physical attacks on the chips.

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“…This way, we may benefit from the latest technology node but, naturally, have to split the design in such a way that the foundries 1 We acknowledge that the idea for 3D SM was envisioned in 2008 by Tezzaron [31]. Also, there are studies hinting at the benefits of 3D integration for SM [32][33][34][35][36] cannot readily infer the whole layout, even when they are colluding. Once such strong protection is in place, it is economically more reasonable to commission only one foundry.…”

Section: D Integration: Our Concept For Ip Protection In the Next Dimentioning

confidence: 99%

Best of both worlds

Patnaik¹,

Ashraf²,

Sinanoglu³

et al. 2018

Proceedings of the International Conference on Computer-Aided Design

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With the globalization of manufacturing and supply chains, ensuring the security and trustworthiness of ICs has become an urgent challenge. Split manufacturing (SM) and layout camouflaging (LC) are promising techniques to protect the intellectual property (IP) of ICs from malicious entities during and after manufacturing (i.e., from untrusted foundries and reverse-engineering by end-users). In this paper, we strive for "the best of both worlds, " that is of SM and LC. To do so, we extend both techniques towards 3D integration, an up-and-coming design and manufacturing paradigm based on stacking and interconnecting of multiple chips/dies/tiers.Initially, we review prior art and their limitations. We also put forward a novel, practical threat model of IP piracy which is in line with the business models of present-day design houses. Next, we discuss how 3D integration is a naturally strong match to combine SM and LC. We propose a security-driven CAD and manufacturing flow for face-to-face (F2F) 3D ICs, along with obfuscation of interconnects. Based on this CAD flow, we conduct comprehensive experiments on DRC-clean layouts. Strengthened by an extensive security analysis (also based on a novel attack to recover obfuscated F2F interconnects), we argue that entering the next, third dimension is eminent for effective and efficient IP protection.

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Security Threats and Countermeasures in Three-Dimensional Integrated Circuits

Cited by 21 publications

References 27 publications

A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

Improving the Physical Security of Microchip

Best of both worlds

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