SEESAW: Using Superpages to Improve VIPT Caches

Parasar, Mayank; Bhattacharjee, Abhishek; Krishna, Tushar

doi:10.1109/isca.2018.00026

Cited by 17 publications

(5 citation statements)

References 25 publications

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“…• No more TLB misses (as there is no longer a TLB) • ∼15% energy savings on chip [10,25,29,30,45,46,48,71,80,92]. • Area savings, assuming you remove the paging hardware, that are on par with the size of an L1 cache [12].…”

Section: Benefits Of Carat-based Systemsmentioning

confidence: 99%

“…The hardware structures supporting the traditional address translation model (per-core DTLBs, ITLBs, STLBs, separate structures for different page sizes, nested TLBs, quad pagewalkers, walker caches) together require almost as much area as L1 caches [12]. A TLB consumes a significant energy [25,48,71,92], and is a thermal hot spot [73]. Early studies find TLB power consumption is as high as 15-17% of the chip's power [45,46].…”

Section: Introductionmentioning

confidence: 99%

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CARAT CAKE: replacing paging via compiler/kernel cooperation

Suchy

Ghosh

Kersnar

et al. 2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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Virtual memory, specifically paging, is undergoing significant innovation due to being challenged by new demands from modern workloads. Recent work has demonstrated an alternative softwareonly design that can result in simplified hardware requirements, even supporting purely physical addressing. While we have made the case for this Compiler-And Runtime-based Address Translation (CARAT) concept, its evaluation was based on a user-level prototype. We now report on incorporating CARAT into a kernel, forming Compiler-And Runtime-based Address Translation for CollAborative Kernel Environments (CARAT CAKE). In our implementation, a Linux-compatible x64 process abstraction can be based either on CARAT CAKE, or on a sophisticated paging implementation. Implementing CARAT CAKE involves kernel changes and compiler optimizations/transformations that must work on all code in the system, including kernel code. We evaluate CARAT CAKE in comparison with paging and find that CARAT CAKE is able to achieve the functionality of paging (protection, mapping, and movement properties) with minimal overhead. In turn, CARAT CAKE allows significant new benefits for systems including energy savings, larger L1 caches, and arbitrary granularity memory management.

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Section: Benefits Of Carat-based Systemsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

CARAT CAKE: replacing paging via compiler/kernel cooperation

Suchy

Ghosh

Kersnar

et al. 2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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“…In summary, leveraging the capacious transient persistence domain made of CPU caches enables Hercules with high adaptability to various pmem products. a VIPT cache [57,94]. TransTags thus cost 3.9% ( 22 48+64×8 ) more space.…”

Section: The Impacts Of Factors On Herculesmentioning

confidence: 99%

Enabling Atomic Durability for Persistent Memory with Transiently Persistent CPU Cache

Ye¹,

Chen²,

Jiang³

et al. 2022

Preprint

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Persistent memory (pmem) products bring the persistence domain up to the memory level. Intel recently introduced the eADR feature that guarantees to flush data buffered in CPU cache to pmem on a power outage, thereby making the CPU cache a transient persistence domain. Researchers have explored how to enable the atomic durability for applications' in-pmem data. In this paper, we exploit the eADR-supported CPU cache to do so. A modified cache line, until written back to pmem, is a natural redo log copy of the in-pmem data. However, a write-back due to cache replacement or eADR on a crash overwrites the original copy. We accordingly develop Hercules, a hardware logging design for the transaction-level atomic durability, with supportive components installed in CPU cache, memory controller (MC), and pmem. When a transaction commits, Hercules commits on-chip its data staying in cache lines. For cache lines evicted before the commit, Hercules asks the MC to redirect and persist them into inpmem log entries and commits them off-chip upon committing the transaction. Hercules lazily conducts pmem writes only for cache replacements at runtime. On a crash, Hercules saves metadata and data for active transactions into pmem for recovery. Experiments show that, by using CPU cache for both buffering and logging, Hercules yields much higher throughput and incurs significantly fewer pmem writes than state-of-the-art designs.

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“…For example, virtual memory might be allocated at 2MB chunks, while physical memory is allocated in 4KB frames. With a larger V2M translation granularity, virtual and Midgard addresses share more bits thereby increasing the L1 set-index bits known prior to translation, ameliorating a limitation of modern VIPT (and our VIMT) cache hierarchies and allowing the L1 cache to scale in capacity [45]. Implementations of guard pages [21], [52] can also be improved with Midgard.…”

Section: E Other Conceptual Benefitsmentioning

confidence: 99%

Rebooting Virtual Memory with Midgard

Gupta¹,

Bhattacharyya²,

et al. 2021

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)

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Computer systems designers are building cache hierarchies with higher capacity to capture the ever-increasing working sets of modern workloads. Cache hierarchies with higher capacity improve system performance but shift the performance bottleneck to address translation. We propose Midgard, an intermediate address space between the virtual and the physical address spaces, to mitigate address translation overheads without program-level changes.Midgard leverages the operating system concept of virtual memory areas (VMAs) to realize a single Midgard address space where VMAs of all processes can be uniquely mapped. The Midgard address space serves as the namespace for all data in a coherence domain and the cache hierarchy. Because real-world workloads use far fewer VMAs than pages to represent their virtual address space, virtual to Midgard translation is achieved with hardware structures that are much smaller than TLB hierarchies. Costlier Midgard to physical address translations are needed only on LLC misses, which become much less frequent with larger caches. As a consequence, Midgard shows that instead of amplifying address translation overheads, memory hierarchies with large caches can reduce address translation overheads.Our evaluation shows that Midgard achieves only 5% higher address translation overhead as compared to traditional TLB hierarchies for 4KB pages when using a 16MB aggregate LLC. Midgard also breaks even with traditional TLB hierarchies for 2MB pages when using a 256MB aggregate LLC. For cache hierarchies with higher capacity, Midgard's address translation overhead drops to near zero as secondary and tertiary data working sets fit in the LLC, while traditional TLBs suffer even higher degrees of address translation overhead.

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SEESAW: Using Superpages to Improve VIPT Caches

Cited by 17 publications

References 25 publications

CARAT CAKE: replacing paging via compiler/kernel cooperation

CARAT CAKE: replacing paging via compiler/kernel cooperation

Enabling Atomic Durability for Persistent Memory with Transiently Persistent CPU Cache

Rebooting Virtual Memory with Midgard

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