Segmentation Method for Modeling Heterogeneous Components to Suppress Broadband Simultaneous Switching Noise on a Multilayer Structure

Lin, Ding‐Bing; Lin, Han-Chang; Zheng, Lin-Zong; Wang, Tse-Hsuan

doi:10.1109/tcpmt.2022.3165693

Cited by 4 publications

(1 citation statement)

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“…Parasitic inductance in the PDN of the high-speed interface, which often contains continuously switching signals at a very high data rate of up to 4.8 Gbps in package and multilayer printed circuit boards, causes SSN that adversely affects the performance of the interface [2]. At high data rates, the de-coupling capacitors, which are traditionally used to reduce or mitigate SSN, are ineffective [3]. Furthermore, quantifying SSN is typically complicated due to its heavy dependence on the physical geometry of the system [4].…”

Section: Introductionmentioning

confidence: 99%

Suppression of Simultaneous Switching Noise Using Embedded Capacitor Method in High-Speed Systems

Saini,

Agarwal

2023

ijmst

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Gbps signals are commonly used in modern high-speed IO designs. These systems require a high level of signal accuracy. However, these signals can cause current fluctuations at high frequencies due to parasitic inductance on the package and board, leading to significant changes in supply voltage. DDRX interfaces that transmit data up to 4.8 Gbps induce simultaneous switching noise (SSN) in the voltage regulator module (VRM). One of the adverse effects of SSN is timing jitter, also known as power supply-induced jitter. The amount of SSN is directly proportional to the number of signals on a parallel bus. Discrete capacitors may not be effective in reducing SSN impact when data is transmitted at high speeds. The current approach used to predict and evaluate errors in SSNs relies on the designer's expertise, which requires accurate estimates of packaging parasitic. In this paper, a practical approach to lessen SSN is presented through the use of embedded capacitors placed between planes and optimizing discrete capacitors by connecting them in a way that measures the impact of supply noise on the I/O transistor circuit performance at the DDRX interface. Two boards were designed, evaluated, and subsequently compared their results.

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Section: Introductionmentioning

confidence: 99%