Selection of silicon wafer for power devices and the influence of crystal defects including impurities

Abstract

Silicon wafers used as starting materials are significantly different in MOS‐LSIs and power devices, because each device requires a specific structure. For power devices, FZ wafers or epitaxial wafers with a thick epitaxial layer are widely used. Epitaxial wafers are advantageous with respect to low breakdown voltage devices, and FZ wafers are advantageous for high breakdown voltage devices. The influence of COPs formed during CZ crystal growth on highly miniaturized MOS‐LSIs is significant; however, COPs do not pose a problem to power devices prepared from FZ or epitaxial wafers. BMDs and slip dislocations have caused device failures on power devices where the device operation layer is deep and the process temperature is high. On the other hand, misfit dislocations which are generated with high concentration do not introduce device failures. Failure due to physical contamination is observed when Fe has introduced a failure to the power device. Cu/pit failures occur due to chemical contamination by Cu only for more highly miniaturized MOS‐LSIs, but are not a problem for power devices whose miniaturization level is not required as that for MOS‐LSIs. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

The influence of flash lamp annealing on the minority carrier lifetime of Czochralski silicon wafers

“…Lifetimes > 100 μs are required for a sufficiently low leakage current in power devices [2]. Until now, the reduction of interstitial oxygen by using float zone (FZ) silicon or epitaxial silicon wafers, is the only solution to circumvent the problem [2]. Therefore, it is desirable to suppress oxygen precipitation during thermal processing in order to make Czochralski silicon a suitable substrate for such applications.…”

“…The BMDs increase the leakage current as the result of their deep levels in the band gap. Lifetimes > 100 μs are required for a sufficiently low leakage current in power devices [2]. Until now, the reduction of interstitial oxygen by using float zone (FZ) silicon or epitaxial silicon wafers, is the only solution to circumvent the problem [2].…”

Assessment of Stacking Faults in Silicon Carbide Crystals

“…Some crystal defects are fatal to devices, whereas others have no adverse effects. (3) In the development of SiC crystal manufacturing technologies, it is important to develop methods of detecting and reducing defects that are detrimental to devices. Stacking faults in SiC have been reported to degrade the characteristics of bipolar devices.…”

Comparison of the Impact of Thermal Treatments on the Second and on the Millisecond Scales on the Precipitation of Interstitial Oxygen

“…Lifetimes >100 μs are required for a sufficiently low leakage current in power devices. 1 Until now, the reduction of interstitial oxygen, i. e. using float zone (FZ) silicon or epitaxial silicon wafers, is the only solution to circumvent the problem. 1 Rapid thermal annealing (RTA) is a widely used thermal pretreatment to create a well-defined internally gettering bulk defect zone and a defect denuded zone below the surface.…”

“…1 Until now, the reduction of interstitial oxygen, i. e. using float zone (FZ) silicon or epitaxial silicon wafers, is the only solution to circumvent the problem. 1 Rapid thermal annealing (RTA) is a widely used thermal pretreatment to create a well-defined internally gettering bulk defect zone and a defect denuded zone below the surface. 2 This is possible because the precipitation of interstitial oxygen strongly depends on the supersaturation of intrinsic point defects.…”