Selective clock gating by using wasting toggle rate

Power reduction is nowadays becoming the first consideration in VLSI design. Low power is one of major concerns in deeply scaled CMOS technologies. There have been many methods in very wide rang to achieve this objective. And the Register-Transfer level (RTL) has become the most effective stage in low power VLSI design, according to the significant power optimization impact and accurate power estimation. In this paper, some respective low power design techniques at RTL are re-investigated at tsmc 45 nanometer CMOS technology. Clock gating (CG) is one of the most widely used and effective technique in RTL low power design. Without the enable signal, bus-specific clock gating (BSC) and threshold-based clock gating (TCG) are considered. Also an improved active-driven optimized bus-specific clock gating (OBSC) is proposed in our laboratory. When the enable signal is taken into account, this paper explains localexplicit clock gating (LECG), enhanced clock gating (ECG), waste-toggle-rate-based (WTR) clock gating and the single comparator-based clock gating (SCCG) techniques. Operand isolation is another useful design technique for reducing the power consumption by blocking some redundant operations. Memory splitting is an effective design solution for low power design as well. These techniques have been experimented by using tsmc 45nm technology library and the proposed low-power RTL techniques are evaluated at gate level with logic synthesis results.

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“…[4] This paper explains some representative low power techniques at RTL, other techniques can be referred to any of excellent references.…”

Section: Introductionmentioning

confidence: 99%

“…Clock gating (CG) is the most widely used and effective technique at RTL. Two typical non-CG circuits are mentioned in [4] as shown in Fig. 1.…”

Section: Introductionmentioning

confidence: 99%

Automatic Register Transfer level CAD tool design for advanced clock gating and low power schemes

Zhang

Tong

et al. 2012

2012 International SoC Design Conference (ISOCC)

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“…5, combines the gating circuits in BSC and LECG so that the clock signal of the register is gated as long as its toggle is waste [9]. Besides the advantages incurred by the low en signal in a significant percentage of the clock periods or the low signal switching activity, this gating circuit which is more complex than LECG incurs more power consumption when the situations aforementioned do not emerge.…”

Section: Fig 4 Bus Specific Clock Gatingmentioning

confidence: 99%

“…Two typical non-CG circuits are mentioned in [9] as shown in Fig. 3(a) is the circuit without enable signal while the other one is with enable signal Without the enable signal, this paper explains bus-specific clock gating (BSC) [10], threshold-based clock gating (TCG) [11] and optimized bus-specific clock gating (OBSC) Fig.…”

Section: Fig 2 Transition In Inverter Input Leading To Switching Powermentioning

confidence: 99%

“…3(a) is the circuit without enable signal while the other one is with enable signal Without the enable signal, this paper explains bus-specific clock gating (BSC) [10], threshold-based clock gating (TCG) [11] and optimized bus-specific clock gating (OBSC) Fig. 3(b), includes local-explicit clock gating (LECG) [9], enhanced clock gating (ECG) [9], waste-toggle-rate-based (WTR) clock gating [9] and the single comparator-based clock gating (SCCG) [13] techniques. Bus-specific clock gating (BSC) is as shown in Fig.…”

Section: Fig 2 Transition In Inverter Input Leading To Switching Powermentioning

confidence: 99%

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Subword Partition based Data Driven Clock Gating Scheme for Low Power VLSI Design

Ranganayakulu¹,

Satyaprasad²

2014

IJCA

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The low power optimization has been major concern in VLSI design from last two decades. The work presented here analyzes various clock gating based power optimization techniques in the context of digital signal processing applications. The clock gating based techniques with architecture level optimization possibilities are discussed. A novel method for data specific clock gating based on subword partition is developed and same is verified on Transposed FIR filter structure. The generic VHDL models of subword datapath based FIR architectures are used along with Xilinx Vivado power and performance analysis tools for validation. The results show power optimization upto 47% for narrowband input signal conditions on Virtex-6 Lx240T FPGA. The research shows a promising direction of power optimization technique, which can be used for wide range of signal processing applications. General TermsSubword partitioning technique.

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A Reconfigurable CNN-Based Accelerator Design for Fast and Energy-Efficient Object Detection System on Mobile FPGA

Kim

Choi

2023

IEEE Access

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In limited-resource edge computing circumstances such as on mobile devices, IoT devices, and electric vehicles, the energy-efficient optimized convolutional neural network (CNN) accelerator implemented on mobile Field Programmable Gate Array (FPGA) is becoming more attractive due to its high accuracy and scalability. In recent days, mobile FPGAs such as the Xilinx PYNQ-Z1/Z2 and Ultra96, definitely have the advantage of scalability and flexibility for the implementation of deep learning algorithm-based object detection applications. It is also suitable for battery-powered systems, especially for drones and electric vehicles, to achieve energy efficiency in terms of power consumption and size aspect. However, it has the low and limited performance to achieve real-time processing. In this article, optimizing the accelerator design flow in the register-transfer level (RTL) will be introduced to achieve fast programming speed by applying low-power techniques on FPGA accelerator implementation. In general, most accelerator optimization techniques are conducted on the system level on the FPGA. In this article, we propose the reconfigurable accelerator design for a CNN-based object detection system on the register-transfer level on mobile FPGA. Furthermore, we present RTL optimization design techniques that will be applied such as various types of clock gating techniques to eliminate residual signals and to deactivate the unnecessarily active block. Based on the analysis of the CNN-based object detection architecture, we analyze and classify the common computing operation components from the Convolutional Neuron Network, such as multipliers and adders. We implement a multiplier/adder unit to a universal computing unit and modularize it to be suitable for a hierarchical structure of RTL code. The proposed system design was tested with Resnet-20 which has 23 layers and it was trained with the dataset, CIFAR-10 which provides a test set of 10,000 images in several formats, and the weight data we used for this experiment was provided from Tensil. Experimental results show that the proposed design process improves the power efficient consumption, hardware utilization, and throughput by 16%, up to 58%, and 15%, respectively.INDEX TERMS FPGA accelerator, CNN accelerator, RT level design techniques, low power techniques, reconfigurable accelerator, CNN-based object detection, low power consumption, high performance, mobile FPGA.

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Selective clock gating by using wasting toggle rate

Cited by 6 publications

References 6 publications

Automatic Register Transfer level CAD tool design for advanced clock gating and low power schemes

Automatic Register Transfer level CAD tool design for advanced clock gating and low power schemes

Subword Partition based Data Driven Clock Gating Scheme for Low Power VLSI Design

A Reconfigurable CNN-Based Accelerator Design for Fast and Energy-Efficient Object Detection System on Mobile FPGA

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