Selective vapor phase etching of SiGe versus Si by HCl

Yamamoto, Yuji; Kopke, K.; Tillack, Bernd

doi:10.1016/j.tsf.2008.08.095

Cited by 12 publications

(10 citation statements)

References 7 publications

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“…The cavity was formed by selective Si sidewall etching 11 of a mesa-patterned SiO 2 / Si / buried oxide stack. High quality and smooth Ge surface without using chemical mechanical polishing process are demonstrated.…”

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confidence: 99%

“…In this study, a technique of high quality local GeOI fabrication using selective growth of Ge to lateral direction in cavity covered by SiO 2 is presented. The cavity was formed by selective Si sidewall etching 11 of a mesa-patterned SiO 2 / Si / buried oxide stack. High quality and smooth Ge surface without using chemical mechanical polishing process are demonstrated.…”

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confidence: 99%

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Selective Lateral Germanium Growth for Local GeOI Fabrication

Yamamoto¹,

Schubert²,

Reich³

et al. 2014

ECS J. Solid State Sci. Technol.

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High quality local Germanium-on-oxide (GeOI) wafers are fabricated using selective lateral germanium (Ge) growth technique by a single wafer reduced pressure chemical vapor deposition system. Mesa structures of 300 nm thick epitaxial silicon (Si) interposed by SiO2 cap and buried oxide are prepared. HCl vapor phase etching of Si is performed prior to selective Ge growth to remove a part of the epitaxial Si to form cavity under the mesa. By following selective Ge growth, the cavity was filled. Cross section TEM shows dislocations of Ge which are located near Si / Ge interface only. By plan view TEM, it is shown that the dislocations in Ge which direct to SiO2 cap or to buried-oxide (BOX) are located near the interface of Si and Ge. The dislocations which run parallel to BOX are observed only in [110] and [1–10] direction resulting Ge grown toward [010] direction contains no dislocations. This mechanism is similar to aspect-ratio-trapping but here we are using a horizontal approach, which offers the option to remove the defective areas by standard structuring techniques. A root mean square of roughness of ∼0.2 nm is obtained after the SiO2 cap removal. Tensile strain in the Ge layer is observed due to higher thermal expansion coefficient of Ge compared to Si and SiO2.

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confidence: 99%

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confidence: 99%

Selective Lateral Germanium Growth for Local GeOI Fabrication

Yamamoto¹,

Schubert²,

Reich³

et al. 2014

ECS J. Solid State Sci. Technol.

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“…The commonly used GPE is a HF vapor process. Recently, GAA transistors have been manufactured by using HCl vapor process as well [130][131][132][133][134][135][136][137][138][139][140][141][142].…”

Section: Gate Processmentioning

confidence: 99%

The Challenges of Advanced CMOS Process from 2D to 3D

Radamson

Zhang

et al. 2017

Applied Sciences

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Abstract:The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.

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“…Therefore a high selectivity between Si and Si 1-x Ge x is needed. Different methods for selective etching are have been-known, like Electron Cyclotron Resonance (ECR) plasma etching [15], Reactive ion etching (RIE) [16] or selective vapor phase etching with HCl using thermal CVD processes performed in a CVD tool [17,18]. High temperatures (650 -750°C) are needed to achieve selectivity around 5 for x=0.2 [17].…”

Section: Introductionmentioning

confidence: 99%

“…Different methods for selective etching are have been-known, like Electron Cyclotron Resonance (ECR) plasma etching [15], Reactive ion etching (RIE) [16] or selective vapor phase etching with HCl using thermal CVD processes performed in a CVD tool [17,18]. High temperatures (650 -750°C) are needed to achieve selectivity around 5 for x=0.2 [17]. And, HF:PAA solution, HF:HNO 3 solution, HF:CH 3 COOH:HNO 3 or H 2 SO 4 solution and HF:H 2 O 2 :CH 3 COOH solution were used for wet etching with a great selectivity compared to Si [19][20][21].…”

Section: Introductionmentioning

confidence: 99%

Selective Chemical Wet Etching of Si_0.8Ge_0.2/Si Multilayer

Kil¹,

Yang²,

Kang³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-We investigate the effect of the ageing time and etching time on the etching rate of SiGe mixed etching solution, namely 1 vp HF (6%), 2 vp H 2 O 2 (30%) and 3 vp CH 3 COOH (99.8%). For this etching solution, we found that the etch rate of SiGe layer is saturated after the ageing time of 72 hours, and the selectivity of Si 0.8 Ge 0.2 layer and Si layer is 20:1 at ageing time of 72 hours. The collapse was appeared at the etching time of 9min with etching solution of after saturation ageing time.

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Selective vapor phase etching of SiGe versus Si by HCl

Cited by 12 publications

References 7 publications

Selective Lateral Germanium Growth for Local GeOI Fabrication

Selective Lateral Germanium Growth for Local GeOI Fabrication

The Challenges of Advanced CMOS Process from 2D to 3D

Selective Chemical Wet Etching of Si_0.8Ge_0.2/Si Multilayer

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Selective vapor phase etching of SiGe versus Si by HCl

Cited by 12 publications

References 7 publications

Selective Lateral Germanium Growth for Local GeOI Fabrication

Selective Lateral Germanium Growth for Local GeOI Fabrication

The Challenges of Advanced CMOS Process from 2D to 3D

Selective Chemical Wet Etching of Si0.8Ge0.2/Si Multilayer

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Selective Chemical Wet Etching of Si_0.8Ge_0.2/Si Multilayer