Self-Adaptive Learning Using Test Case Selection in Grammatical Evolution for Automatic Design of Digital Circuit

Abstract

In today’s digital age, the demand for increasingly complex digital circuits spans applications ranging from watches to spacecraft. To meet this demand, circuit design automation using Artificial Intelligence (AI) has emerged as a key solution due to manual processes’ time-consuming and error-prone nature. Among AI techniques, Evolutionary Algorithm (EA), notably Grammatical Evolution(GE), have shown promise. However, the computational cost of these algorithms remains a significant challenge, particularly concerning scalability and the high volume of test cases required for circuit design and synthesis. Balancing the trade-off between the necessity for extensive training data and the computational overhead of GE is crucial. The exponential increase in data volume with circuit complexity presents a challenging obstacle. While utilizing complete training data may ensure accurate circuit design, practical constraints often limit its feasibility. Furthermore, reducing data through selection risks compromising crucial information, while using complete data incurs prohibitively high training costs. This study proposes a novel self-adaptive learning approach within the framework of EAs to utilize training data adaptively and effectively. Our objective is to achieve comparable circuit solutions within a reduced runtime. We apply this technique to GE, naming it Self-adaptive Learning in GE (SLIG). SLIG divides the training data into subsets based on decreasing diversity, ensuring that the model is exposed to highly diverse scenarios early in the evolutionary process and gradually incorporating less diverse data. This method is rigorously evaluated across four digital circuits. The circuits are designed using Hardware Description Language (HDL), facilitating precise and efficient design, simulation, and synthesis. Experimental and statistical results indicate its effectiveness in producing comparable or superior results compared to standard GE, as measured in terms of circuits’ test scores, solution size, runtime efficiency, and performance parameters evaluated by the Cadence Genus Synthesis solution tool.