Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects

Lehtonen, Teijo; Wolpert, David; Liljeberg, Pasi; Plosila, Juha; Ampadu, Paul

doi:10.1109/tvlsi.2009.2013711

Cited by 73 publications

(41 citation statements)

References 21 publications

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“…If a data packet is found corrupted, it can either be corrected using the redundant code or retransmitted [19]. On the other hand, permanent faults can be checked off-line using self-test mechanisms, such as scan chains [21], or detected on-line by searching persistent errors using certain coding schemes [12,7]. Although permanent faults cannot be recovered, a network may survive with reduced resources.…”

Section: Related Workmentioning

confidence: 99%

“…Although permanent faults cannot be recovered, a network may survive with reduced resources. The faulty components can be replaced with spares [12] or isolated using adaptive routing algorithms [21,7].…”

Section: Related Workmentioning

confidence: 99%

“…However, they are extremely vulnerable to permanent faults because these faults break the handshake protocol and cause deadlocks. Unlike synchronous circuits, where redundant coding schemes can be employed to detect permanently faulty links or switches [12,9,7], the deadlock in QDI NoCs prohibits the propagation of data and therefore disables any data checks. Although off-line scan techniques can locate permanent faults [17], detecting them on-line remains difficult.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip

Song

Zhang

Garside

2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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Asynchronous networks on chip (NoCs) are promising candidates for supporting the enormous communication needed by future many-core systems due to their low-energy and high-speed. Similar to synchronous NoCs, asynchronous NoCs are vulnerable to faults but their fault-tolerance is not studied adequately, especially the quasi-delay insensitive (QDI) NoCs. One of the key issues neglected by most designers is that permanent faults in QDI NoCs cause deadlocks, which cripples the traditional fault-tolerant techniques using redundant codes. A novel detection method has been proposed to locate the faulty link in a QDI NoC according to a common pattern shared by all fault-related deadlocks. It is shown that this method introduces low hardware overhead and reports permanently faulty links with a short delay and guaranteed accuracy.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip

Song

Zhang

Garside

2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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“…Permanent faults may happen at runtime with the ageing process and will never disappear [5]. The resulting permanent errors will bring lifetime reliability problems, even causing chips to be discarded.…”

Section: Introductionmentioning

confidence: 99%

An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults

Zhang

Song

Garside

et al. 2014

2014 20th IEEE International Symposium on Asynchronous Circuits and Systems

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Abstract-Asynchronous circuits have been used to implement Networks-on-Chip (NoCs), resulting in asynchronous NoCs where the links are usually implemented as quasi-delay-insensitive (QDI) pipelines to tolerate delay variations. With the ageing process of circuits, permanent faults may happen on links at runtime, causing both data errors and deadlocks of the network. This paper presents an asynchronous Spatial Division Multiplexing (SDM) NoC which tolerates permanent faults on the QDI links. Using a time-out mechanism, a general fault-detection technique can locate the permanent fault in the deadlocked NoC. To recover the network, a Drain&Release technique releases faultfree network resources on the deadlocked path. The SDM NoC physically divides every link and buffer into multiple independent virtual circuits. By configuring the switch allocator, the faulty virtual circuit is blocked so that it will not be allocated to any packets. The succeeding traffic requesting the same link will go through other fault-free virtual circuits and the network function is recovered. With regard to intermittent faults, the previously blocked virtual circuit can be resumed when the fault disappears. Experimental results show the asynchronous SDM NoC can detect and recover from permanent faults with reasonable overhead.

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“…[32][33] based on the use of the negative group delay circuit whose the principle is developed in [34][35] has been introduced. Moreover, accurate, optimized and also easy to implement models enabling the prediction of these unwanted effects are indispensable [36][37][38][39]. In this scope, new generations of design strategies and commercial numerical tools for simulation and characterization of various 3-D structure geometries permitting to ensure the signal fidelity at Gbits/s-speeds were recently reported [40][41][42][43][44].…”

Section: Introductionmentioning

confidence: 99%

Delay modeling of high-speed distributed interconnect for the signal integrity prediction

Raveloa

2012

Eur. Phys. J. Appl. Phys.

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Abstract:A relevant modelling method of distributed interconnect line for the high-speed signal integrity (SI) application is introduced in this paper. By using the microwave and transmission line (TL) theory, the interconnect lines are assumed as its distributed RLC-model. Then, based-on the transfer matrix analysis, the second order global transfer function of the interconnect network comprised of the TL driven by voltage source including its internal resistance and the impedance load is expressed. Thus, mathematical analysis enabling the physical SI parameters extraction was established by using the transient response of the loaded line. To verify the relevance of the developed model, RC-and RLC-lines excited by square-wave-pulse with 10-Gbits/s-rate were investigated. So, comparisons with SPICE-computations were performed. As results, transient responses perfectly well-correlated to the reference SPICE-models were evidenced. As application of the introduced model, evaluations of rise-/fall-times, propagation delays, signal attenuations and even the settling times were realized for different values of TL parameters. Compared to other methods, the computation execution time and data-memory consumed by the program implementing the proposed delay modelling-method algorithm are much better.

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Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects

Cited by 73 publications

References 21 publications

On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip

On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip

An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults

Delay modeling of high-speed distributed interconnect for the signal integrity prediction

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