Self-aligned double-patterning layout decomposition for two-dimensional random metals for sub-10-nm node design

Ban, Yongchan; Pan, David Z.

doi:10.1117/1.jmm.14.1.011004

Cited by 5 publications

(2 citation statements)

References 24 publications

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“…Finally, double patterning techniques are not limited to nanosheets and are able to produce nanostructures of arbitrary complexity. [ 45 ] Our results open up new routes toward integration of ultra‐scaled 2D materials devices in future electronics and can assist future optimization efforts in this exciting research field.…”

Section: Discussionmentioning

confidence: 98%

Self‐Expansion Based Multi‐Patterning for 2D Materials Fabrication beyond the Lithographical Limit

Borhade,

Chen,

Chen

et al. 2023

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Two‐dimensional (2D) materials are promising successors for silicon transistor channels in ultimately scaled devices, necessitating significant research efforts to study their behavior at nanoscopic length scales. Unfortunately, current research has limited itself to direct patterning approaches, which limit the achievable resolution to the diffraction limit and introduce unwanted defects into the 2D material. The potential of multi‐patterning to fabricate 2D materials features with unprecedented precision and low complexity at large scale is demonstrated here. By combining lithographic patterning of a mandrel and bottom‐up self‐expansion, this approach enables pattern resolution one order of magnitude below the lithographical resolution. In‐depth characterization of the self‐expansion double patterning (SEDP) process reveals the ability to manipulate the critical dimension with nanometer precision through a self‐limiting and temperature‐controlled oxidation process. These results indicate that the SEDP process can regain the quality and morphology of the 2D material, as shown by high‐resolution microscopy and optical spectroscopy. This approach is shown to open up new avenues for research into high‐performance, ultra‐scaled 2D materials devices for future electronics.

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Section: Discussionmentioning

confidence: 98%

Self‐Expansion Based Multi‐Patterning for 2D Materials Fabrication beyond the Lithographical Limit

Borhade,

Chen,

Chen

et al. 2023

Small

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“…Although SAMP approaches alleviate some EPE challenges, they do come with additional limitations related to design rule and layout restrictions. 245 They are also limited in some regards by various attributes of the spacer material. Specifically, any thickness variation or surface roughness in the spacer material can directly impact, respectively, the CD and line edge/width roughness (LER/LWR) of the final formed feature.…”

Section: Spacers and Hard Masks -The Disappearing Dielectricsmentioning

confidence: 99%

Review—Beyond the Highs and Lows: A Perspective on the Future of Dielectrics Research for Nanoelectronic Devices

Jenkins

Austin

Conley

et al. 2019

ECS J. Solid State Sci. Technol.

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High-dielectric constant (high-k) gate oxides and low-dielectric constant (low-k) interlayer dielectrics (ILD) have dominated the nanoelectronic materials research scene over the past two decades, but they have recently reached a state of maturity and perhaps the limits of their scaling. Based on this, there is a need for a systematic review summarizing not only the historic research and achievements on high-k and low-k dielectrics, but also emerging device applications as well as an outlook of future challenges. We begin by first reviewing the factors that drove the emergence of low-k and high-k materials in nanoelectronics as ILD and gate dielectric materials, respectively, and the challenges and limits these materials ultimately approached in terms of permittivity scaling. We then illustrate that gate dielectric and ILD applications represent just a small fraction of the numerous dielectrics utilized in present day nanoelectronic products where permittivity scaling is now being increasingly demanded for materials such as dielectric spacers, trench isolation, and etch stopping layers. We conclude by examining the numerous new applications for dielectric materials that are emerging as the semiconductor industry transitions to novel patterning schemes, prepares for life post CMOS scaling, and explores ways to natively embed device functionality in the metal interconnect. For the former, we specifically examine the “colorful” requirements for the various enabling dielectric hardmask and spacer materials utilized in pitch division-multi-pattern processes and then discuss the role that selective area deposition of dielectrics and metals could play in reducing the complexity of such patterning processes. For the latter, we review the use of both high-k and low-k dielectrics in various metal-insulator-metal (MIM) structures as Fermi level de-pinning layers, tunnel diodes, and back-end-of-line (BEOL) compatible capacitive and resistive switching random access memory (ReRAM) elements. We further examine how dielectrics can hinder or aid new forms of computing such as quantum and neuromorphic in reaching their full potential. In conclusion, we find that while the field of dielectrics has a long history, it remains vibrant with numerous exciting new and old research vectors awaiting further exploration.

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High density hexagonal MTJ array with 72 nm pitch and 30 nm CD by using advanced DRAM patterning solution and ion beam etch

Wang¹,

Xiao²,

Huang³

et al. 2022

AIP Advances

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A hexagonal honeycomb magnetic tunneling junction array with 72 nm pitch and 30 nm MgO critical dimension was successfully fabricated on a 1× nm dynamic random access memory platform by using a mature dynamic random access memory patterning solution and ion beam etch. To our knowledge, both pitch size and critical dimension size are the world’s smallest ones for industrial magnetic tunneling junction arrays. To obtain such a high density and small sized magnetic tunneling junction array, a cross self-aligned double patterning technique, a triple layer hard mask scheme, and an optimized ion beam etch condition were adopted. During the optimization of the ion beam etch process, the dependence of a magnetic tunneling junction pillar profile on ion beam etch parameters for a high density hexagonal magnetic tunneling junction array has also been systematically studied. The depth of oxide recess and the magnetic tunneling junction sidewall angle increased with the ion beam etch amount, while magnetic tunneling junction critical dimension and hard mask remainder thickness decreased with increasing ion beam etch amount.

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Self-aligned double-patterning layout decomposition for two-dimensional random metals for sub-10-nm node design

Cited by 5 publications

References 24 publications

Self‐Expansion Based Multi‐Patterning for 2D Materials Fabrication beyond the Lithographical Limit

Self‐Expansion Based Multi‐Patterning for 2D Materials Fabrication beyond the Lithographical Limit

Review—Beyond the Highs and Lows: A Perspective on the Future of Dielectrics Research for Nanoelectronic Devices

High density hexagonal MTJ array with 72 nm pitch and 30 nm CD by using advanced DRAM patterning solution and ion beam etch

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