2004
DOI: 10.1109/led.2003.823060
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Self-Aligned n-Channel Germanium MOSFETs With a Thin Ge Oxynitride Gate Dielectric and Tungsten Gate

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Cited by 170 publications
(76 citation statements)
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“…[4][5][6] The poor device performance is likely caused by the presence of defects near the semiconductor/dielectric interface, such as germanium dangling bonds (DBs) or vacancies, making the study and characterization of these defects a much needed and timely task.…”
Section: 3mentioning
confidence: 99%
“…[4][5][6] The poor device performance is likely caused by the presence of defects near the semiconductor/dielectric interface, such as germanium dangling bonds (DBs) or vacancies, making the study and characterization of these defects a much needed and timely task.…”
Section: 3mentioning
confidence: 99%
“…Many attempts have been made with different high-K dielectrics including HfO 2 [2], ZrO 2 [3], Al 2 O 3 [4], LaAlO 3 [5] to find a suitable passivation for Ge. Mobilities above 300cm 2 V -1 s -1 have been reported for Ge PMOS while Ge NMOS in the past exhibited poor drive current and low mobility by several demonstrations worldwide [6,7]. Better characterization and understanding of interface traps is required.…”
Section: Introductionmentioning
confidence: 99%
“…For the integration of Ge into such applications, the challenges faced are poor solubility of dopants, large diffusion coefficients, and the incomplete activation of dopants which have led to high off currents and low on-drive currents in transistors. 4 The poor device performances have all stemmed from the large contact resistances found in the source and drain regions. The large contact resistances to n-Ge have been attributed to Fermi level (E F ) pinning near the valence band which results in large Schottky barrier heights (SBH) independent of the metal work function.…”
mentioning
confidence: 99%