Self-Programmable Shared BIST for Testing Multiple Memories

Abstract

Hundreds of memory instances and their high frequency of operation have ruled out the possibility of sharing test structures amongst the embedded memories. This paper discusses the techniques and flow for sharing an embedded memory BIST for the atspeed testing of multiple memories on a typical SoC.

A complete methodology for determining memory BIST optimization under wrappers sharing constraints

“…Reference [6] proposes a hierarchical and distributed approach for BIST and a scheduling which supports the integration of embedded cores with different test requirements. In [4], the authors present a technique for sharing the memory BIST wrapper for at-speed testing of multiples memories placed on a SOC with very low area overhead. It is used to test memories of different sizes using a single BIST system.…”

Memory BIST area estimator using Artificial Neural Networks

“…UILT-in self test (BIST) is the main DFT technique used for memory testing [10,11,12,13]. Compared to other techniques, it is characterized by its good fault coverage, test speed and enabling direct test access to embedded memory; however it increases the area and gives small information for diagnosis.…”

“…How to save test run time and at the same time control the circuit overall area overhead? The problem is that the best estimation of the BIST area overhead, before going far in the design flow, is obtained after RTL synthesis which is time and synthesis license consuming especially when the number of BIST in the design is important leading designers to spend lot of time in exploring BIST strategies [10,11,12,13] and options as bitmap, redundancy, etc… Actually, SOC designers need to have, early during the design flow, an area estimation in order to be able to make some modifications or optimizations to full fit their specifications. Time-to-market constraints push more and more designers to reduce designing time, and SOC is in a large part contributing in this strategy, so it is not acceptable to spend a lot of time calculating BIST area overhead for different architectural configurations.…”