Self-reconfigurable algorithm of WSI sorting network

Horiguchi, Susumu; Numata, I.; Kimura, Miyako

doi:10.1109/icwsi.1991.151723

Cited by 4 publications

(1 citation statement)

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“…Since each module in the k-way bitonic sorter is a bitonic sorter and the interconnections between modules are shuffle connections, it is hard to introduce redundancies into the sorter. The hybrid sorter in [6] is a defect-tolerant and selfreconfigurable sorter [7]. However, since this scheme is not cost This paper is organized as follows.…”

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confidence: 99%

Design and analysis of defect tolerant hierarchical sorting networks

Kuo

Liang

1993

IEEE Trans. VLSI Syst.

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Absbuct-4 novel hierarchid modular sorting network whidi achieves a balance in area-time cost between the odd-even trPnsposition sort and the Mtoalc sort is pmemted. It m"cs less h"e than a singlelevel odd-even sorter and reduces the wire complexity of the bitonic sorter in VLSI or WSI (wafer scale integration) i"cntpti0n. The optimrrl number of kveb in the biemrchy is evaluated and the sorting capability of ea& level is derived to " i v the hardware overhead. The hierarchical sorting network is very regdm in stroetorr and hence is epoy to include defect tolerance capability than any e&lsting sorting network with the time complexity. Redundancy is provided at every level of the hierarchy. Rierprehial ree'onBgurpton is performed '0 40 80 100 120 140 by replacing thedefective eells at the bottom level with thespareeells first, and repeat the 8.w process in the next higher level if there is not enougb rednndmcy at the current level. Yield analysis is performed to d e " &

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confidence: 99%