Self-Repairing Hybrid Adder With Hot-Standby Topology Using Fault-Localization

Akbar, Muhammad Ali; Wang, Bo; Bermak, Amine

doi:10.1109/access.2020.3016427

Cited by 10 publications

(6 citation statements)

References 20 publications

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“…It should be noted that the technique to compare the sum-bit and carryout-bit has been presented in [15] for ripple carry adder, whereas it has not been examined for CLA. The basic architecture of self-checking multiplexer (MUX) design was introduced in [16], which has been improved with reduced transistor count in [17]. To limit the area-overhead of our proposed design, the self-checking MUX and OR gate are implemented using the design presented in [17].…”

Section: B Proposed Self-checking Cla With Fault Localizationmentioning

confidence: 99%

“…The basic architecture of self-checking multiplexer (MUX) design was introduced in [16], which has been improved with reduced transistor count in [17]. To limit the area-overhead of our proposed design, the self-checking MUX and OR gate are implemented using the design presented in [17].…”

Section: B Proposed Self-checking Cla With Fault Localizationmentioning

confidence: 99%

“…Since each NAND gate requires 4 transistors, for a fair comparison, the NAND equivalent circuit of each module based on transistor count is computed and compared with similar approaches used in [12] and [13]. For example, an XOR gate and a self-checking MUX can each be implemented using six transistors [17]. Therefore, each pair of XOR gates and self-checking MUXs have been considered equivalent to three NAND gates.…”

Section: A Area Overheadmentioning

confidence: 99%

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Self-Repairing Carry-Lookahead Adder With Hot-Standby Topology Using Fault-Localization and Partial Reconfiguration

Akbar

Wang

Bermak

2022

IEEE Open J. Circuits Syst.

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In this paper, a self-checking and -repairing carry-lookahead adder (CLA) is proposed with distributed fault detection ability. The presented design with self-checking and fault localization ability requires an area overhead of 69.6% as compared to the conventional CLA. It can handle multiple faults simultaneously without affecting the delay of conventional CLA, with the condition that each module has a single fault at a time. The repairing operation utilizes the hot-standby approach with partial reconfiguration in which the faulty module would be replaced by an accurately functioning module at run-time. The proposed self-repairing adder with high fault coverage requires 161.5% area overhead as compared to conventional CLA design which is 35.3% less as compared to the state-of-the-art partial self-repairing CLA. Moreover, the delay of the proposed 64-bit self-repairing CLA is 40.7% more efficient as compared to conventional ripple carry adder.INDEX TERMS Self-repairing, fault localization, self-checking adder.

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Section: B Proposed Self-checking Cla With Fault Localizationmentioning

confidence: 99%

Section: B Proposed Self-checking Cla With Fault Localizationmentioning

confidence: 99%

Section: A Area Overheadmentioning

confidence: 99%

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Self-Repairing Carry-Lookahead Adder With Hot-Standby Topology Using Fault-Localization and Partial Reconfiguration

Akbar

Wang

Bermak

2022

IEEE Open J. Circuits Syst.

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“…Reconfigurable computing also involves the power of coupling i.e. if there is some programming logic that cannot be mapped onto the Reconfigurable architectures, then they can be executed to some host microprocessors [1]. Numerous coupling techniques can couple devices with the Reconfigurable logic and they are as follows: First, the Reconfigurable architectures can be used as a standalone functional unit with a host coprocessor.…”

Section: Introductionmentioning

confidence: 99%

Performance Improvement for Reconfigurable Processor System Design in IoT Health Care Monitoring Applications

2024

Teh. vjesn.

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This research focuses on critical hardware components of an Internet of Things (IoT) system for reconfigurable processing systems. Single-Instruction Multiple-Data (SIMD) processors have recently been utilized to preprocess data at energy-constrained sensor nodes or IoT gateways, saving significant energy and bandwidth for transmission. Using traditional CPU-based systems to implement machine learning algorithms is inefficient in terms of energy consumption. In the proposed method Single-Instruction Multiple-Data (SIMD) processors are assembled by scaling the largest possible operand value subunits into direct access to the internal memory, where the carry output of each unit is conditionally fed into the next unit based on the implementation of the SIMD Processor design for Internet of Things applications. Each method has evaluated sub-operations that contribute considerably to the overall potential of the design. If the single register file can complete the intended action, a zero (one)-signal is applied to each unit's carry input. Multiplexers combine two or more adders, sending the carry signal from one unit into another if additional units are necessary to compute the sum. The outcome results compare high-speed end device techniques in terms of area and power consumption. The proposed SIMD processor-based IoT healthcare monitoring system with a MIMD processor's performance analysis of comparison clearly demonstrates that the system produces decent outcomes. The suggested system has an area overhead of 85 m 2 , a power usage of 4.10 W, and a time delay of 20 ns.

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“…The self-repairing adders also suffer from carry propagation among various CaSeAs inside it and are widely used in fault recovery systems. Hybrid adders exhibit such properties and are able to locate the place of fault by using the fault localization concept [11]. For the construction of novel memory type adders, traditional CMOS circuits are combined with magnetic memories and achieved a markable improvement compared to previous memory type adders [12].…”

Section: Introductionmentioning

confidence: 99%

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

Battini

Bikshalu²,

Sivani³

2023

Eng. Res. Express

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This paper proposes a novel architecture of novel excess-1 adder basedCarry Select Adder (M2CSA) using single leaf cell i.e., 2-1 Multiplexer. The proposed4-, 8-, 16-, 32-, 64-bit M2CSAs use 2-1 Multiplexers only. The complex gates suchas XOR gates are completely eliminated which exist in existing Carry Select Adders(CaSeAs). A 64-bit M2CSA is distinctly decomposed for maintaining excellent cellregularity that uses one type of 2-1 Multiplexer cell. Ripple carry adder block inexisting designs are replaced with half adders by reducing the carry propagation tocertain extent. At the outset the speed of M2CSA is improved by overcoming carrypropagation through adder blocks, especially in 32- and 64-bit adders. The area isthe major concern for CaSeAs; is also reduced for M2CSAs by maintaining the cellregularity. The M2CSA and existing CaSeAs are designed using Verilog HDL. Thefunctional testing of all the designs is carried out using Cadence NCLaunch. All thedesigns are synthesized & implemented using Cadence Genus and Innovus respectivelyat 90nm technology node. The final ASIC layout of 64-bit M2CSA is more compact interms of area by an average of 17% compared to existing designs. The result analysisand comparison reveal that M2CSAs are better in terms of speed and power dissipationby 20% and 19% respectively. Therefore, M2CSA is best suitable to low-power, low area and high-speed applications

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Self-Repairing Hybrid Adder With Hot-Standby Topology Using Fault-Localization

Cited by 10 publications

References 20 publications

Self-Repairing Carry-Lookahead Adder With Hot-Standby Topology Using Fault-Localization and Partial Reconfiguration

Self-Repairing Carry-Lookahead Adder With Hot-Standby Topology Using Fault-Localization and Partial Reconfiguration

Performance Improvement for Reconfigurable Processor System Design in IoT Health Care Monitoring Applications

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

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