Self-Repairing SRAM Using On-Chip Detection and Compensation

Mojumder, Niladri N.; Mukhopadhyay, Saibal; Kim, Jae‐Joon; Chuang, Ching-Te; Roy, Kaushik

doi:10.1109/tvlsi.2008.2008808

Cited by 8 publications

(10 citation statements)

References 13 publications

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“…Then, we performed MC simulations combined with the mixture importance sampling technique [19] to obtain an approximation to . As there is no process variation technology file available for the predictive technology models, we use a methodology similar to the one presented in [14], [18] transistor from its shifted-nominal value, i.e., , resulting in mismatches among them.…”

Section: B Simulation Methodologymentioning

confidence: 99%

“…On the other hand, the inter-die variations in process parameters cause the mean of the within-die DRV distribution to vary from die to die. For example, the mean of the cells DRV is expected to be larger in dies at the FS (Fast NMOS, Slow PMOS) corner of the process, due to a larger leakage current of pull-down nMOS transistors [18]. As a result, of dies from the FS corner of the process will be larger than that of dies subject to nominal process.…”

Section: B Joint Impact Of the Inter-and Intra-die Variations On Of mentioning

confidence: 99%

“…We can define the average number of failing cells at in a memory array as (18) where is the total number of bit cells in the array. Then, (15) can be approximated as (19) when becomes sufficiently large.…”

Section: Poisson Yield Modelmentioning

confidence: 99%

“…Postsilicon tuning techniques have been introduced in the literature [12]- [18] that allow chip parameters, e.g., clock frequency or operating voltage, to be adjusted after the die has been manufactured, in order to compensate for the specific inter-and intra-die variations that have occurred on that particular die. In this work, we investigate a similar approach as in [15] and [16] to tune the standby supply voltage of each individual die after manufacturing, i.e., postsilicon.…”

Section: Introductionmentioning

confidence: 99%

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Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures

Nourivand

Al-Khalili

Savaria

2012

IEEE Trans. VLSI Syst.

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Lowering the supply voltage of static random access memories (SRAMs) during standby modes is an effective technique to reduce their leakage power consumption. To maximize leakage reductions, it is desirable to reduce the supply voltage as much as possible. SRAM cells can retain their data down to a certain voltage, called the data-retention voltage (DRV). Due to intra-die variations in process parameters, the DRV of cells differ within a single memory die. Hence, the minimum applicable standby voltage to a memory die ( DDLmin ) is determined by the maximum DRV among its constituent cells. On the other hand, inter-die variations result in a die-to-die variation of DDLmin .Applying an identical standby voltage to all dies, regardless of their corresponding DDLmin , can result in the failure of some dies, due to data-retention failures (DRFs), entailing yield losses. In this work, we first show that the yield losses can be significant if the standby voltage of SRAMs is reduced aggressively. Then, we propose a postsilicon standby voltage tuning scheme to avoid the yield losses due to DRFs, while reducing the leakage currents effectively. Simulation results in a 45-nm predictive technology show that tuning standby voltage of SRAMs can enhance data-retention yield by 10%-50%.

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Section: B Simulation Methodologymentioning

confidence: 99%

Section: B Joint Impact Of the Inter-and Intra-die Variations On Of mentioning

confidence: 99%

Section: Poisson Yield Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures

Nourivand

Al-Khalili

Savaria

2012

IEEE Trans. VLSI Syst.

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“…D-ABB possess two major short-comings: 1) Design of analog circuits is a complex task because of the second order effects on design specifications and 2) Since most high-performance analog circuits depend on matched devices, the performance variation caused by this mismatch will be crucial in scaled CMOS technologies. Unlike [6] [8], a self-restoring closedloop compensation technique by monitoring the read stability and writability is discussed in [9].…”

Section: Introductionmentioning

confidence: 99%

A New Sensitivity-Driven Process Variation Aware Self-Repairing Low-Power SRAM Design

Yadav

Dutt

Sharma

2014

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems

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Variation in process parameters results in an appalling number of SRAM failures which jeopardize design yield. These variations are expected to get further aggravate with technology scaling. Adaptive Body Bias (ABB) and Dynamic Voltage Scaling (DVS) are the useful techniques to alleviate the impact of process variation. However, with continued technology scaling, the achievable performance by ABB or DVS alone is becoming limited. In this paper, we propose a process corner based sensitivity-driven approach for self-restoring SRAM design by amalgamating ABB with DVS. More importantly, we leverage the contradiction between read-write stabilities and uneven conduct of inter-die process variation to Noise Margins (NMs) as a blessing of low-power SRAM design. Simulation results based on PTM 32nm CMOS technology quantify the viability and effectiveness of the scheme. Proposed approach meliorate Static Noise Margin (SNM), Read Noise Margin (RNM) and Write Margin (WM) by 12.6%, 59.2% and 6.1%, respectively. In addition, leakage current is reduced by 57.1% and a power redeem of 67.9%, 13.1% and 5.2% is achieved in hold, read and write mode, respectively.

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Variations: Sources and Characterization

Bansal

Rao

2010

Low-Power Variation-Tolerant Design in Nanometer Silicon

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Self-Repairing SRAM Using On-Chip Detection and Compensation

Cited by 8 publications

References 13 publications

Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures

Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures

A New Sensitivity-Driven Process Variation Aware Self-Repairing Low-Power SRAM Design

Variations: Sources and Characterization

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