2006
DOI: 10.1109/tc.2006.61
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Self-stabilizing microprocessor: analyzing and overcoming soft errors

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Cited by 35 publications
(20 citation statements)
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“…Recent work e.g. on scheduling of memory requests [54], transactional memory in multicores [19], and self-stabilizing microprocessors [13], as well as our own work introduced below, confirms that it is indeed possible to utilize distributed algorithms research in the VLSI context. Conversely, results and methods from VLSI-related research, as error-correcting codes, have proved useful e.g.…”
Section: Introductionmentioning
confidence: 53%
“…Recent work e.g. on scheduling of memory requests [54], transactional memory in multicores [19], and self-stabilizing microprocessors [13], as well as our own work introduced below, confirms that it is indeed possible to utilize distributed algorithms research in the VLSI context. Conversely, results and methods from VLSI-related research, as error-correcting codes, have proved useful e.g.…”
Section: Introductionmentioning
confidence: 53%
“…Moreover, the processor executes a fetched command according to its specification [19]{2/3.2}, where the state of the processor when the first fetch starts is arbitrary. The assumption concerning the repeated execution of fetch-decode-execute can be achieved by techniques presented in [11] and [12].…”
Section: System Settingsmentioning
confidence: 99%
“…This assumption is not simple to achieve since both the microprocessor [12] and the operating system should be self-stabilizing, ensuring that eventually the (self-stabilizing) application programs are executed. An elegant composition technique of self-stabilizing algorithms [13] is used here to show that once the underling microprocessor stabilizes the self-stabilizing operating system (which can be started in an arbitrary state) stabilizes, and then the self-stabilizing algorithms that implement the applications, stabilize.…”
Section: Introductionmentioning
confidence: 99%
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“…For example, in [8,9], it has been shown that self-stabilizing algorithms [7], which recover even from massive transient faults, can be employed in VLSI chips. Similarly, in our DARTS 1 project (Distributed Algorithms for Robust Tick-Synchronization), we have implemented a fault-tolerant clocking scheme for SoCs by adapting a simple clock synchronization algorithm to the requirements and constraints of asynchronous digital logic [11].…”
Section: Introductionmentioning
confidence: 99%