Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement

Abstract

Testing digital integrated circuits is generally done using Design-for-Testability (DfT) solutions. Such solutions, however, introduce non-negligible area and timing overheads that can be overcome by adopting functional solutions. In particular, functional test of integrated circuits plays a key role when guaranteeing the device's safety is required during the operative lifetime (in-field test), as required by standards like ISO26262. This can be achieved via the execution of a Self-Test Library (STL) by the device under test (DUT). Nevertheless, developing such test programs requires a significant manual effort, and can be non-trivial when dealing with complex modules. This paper moves the first step in defining a generic and systematic methodology to improve transition delay faults' observability of existing STLs. To do so, we analyze previously devised STLs in order to highlight specific points within test programs to be improved, leading to an increase in the final fault coverage.

Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries

“…The development of test programs for delay faults through an SBST approach has been faced by some works describing methodologies to do so [6], [8], [10]. Regarding TDF specifically, [21] introduces a study on transition delay faults of modern pipelined CPUs that have not been observed throughout the execution of STLs targeting SAFs, focusing on where their effects propagated and stopped inside the DUT. The article introduces two fault groups: User Accessible Register faults (UARs), whose effects reached registers that can be directly observed through instructions from the CPU's instruction set architecture, e.g., the register file, and Hidden Register (HRs) faults, whose effects reached registers non directly controllable, e.g., pipeline registers.…”

“…The article introduces two fault groups: User Accessible Register faults (UARs), whose effects reached registers that can be directly observed through instructions from the CPU's instruction set architecture, e.g., the register file, and Hidden Register (HRs) faults, whose effects reached registers non directly controllable, e.g., pipeline registers. The work in [21] provides some useful insights on what faults to target to improve the final fault coverage, and provides an upper bound on how much the final transition delay fault coverage can be improved. Given three test programs, namely STL1, STL2 and STL3, [21] shows that it is possible to increase their fault coverage by, relatively, 9.15, 17.85 and 8.96 percentile units.…”

“…The work in [21] provides some useful insights on what faults to target to improve the final fault coverage, and provides an upper bound on how much the final transition delay fault coverage can be improved. Given three test programs, namely STL1, STL2 and STL3, [21] shows that it is possible to increase their fault coverage by, relatively, 9.15, 17.85 and 8.96 percentile units. This work, however does not provide strategies to detect them, which is the goal of this paper.…”

“…Moreover, when fault reports are available, understanding why certain faults are not detected (possibly isolating the contribution of FUFs) is not always easy. The work in [21] moves the first step in classifying not-observed transition delay faults, giving some insights on where these fault effects propagated and stopped and defining some upper boundaries on how much the final TDF coverage can be increased.…”

“…In this paper, we propose an automatic and systematic methodology to increase the TDF coverage of STLs, by detecting faults identified in [21] on complex pipelined processor cores, starting from a set of test programs devised for stuck-at faults (SAFs). We choose the transition delay fault model over the path delay one because TDFs are much better supported by both standards and EDA tools than PDFs.…”