Self-testing of multiprocessor systems with regular diagnostic connections

Romankevich, Vitaliy

doi:10.1134/s0005117917020084

Cited by 8 publications

(1 citation statement)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The logical checkability gained development in the theory and practice of creation of the totally selfchecking circuits [18]. Self-checking of these circuits increases structurally-functional checkability in error detection schemes when the self-testing condition is met [19].…”

Section: Related Work Goal and Structure Of The Papermentioning

confidence: 99%

Power-Consumption-Oriented Checkability for Fpga-Based Components of Safety-Related Systems

Drozd¹,

Antoniuk²,

Drozd³

et al. 2019

IJC

View full text Add to dashboard Cite

This paper is dedicated to the problem of the circuit checkability of components in the safety-related systems, which operate objects of the increased risk and are aimed at ensuring safety of both a system and a control object for accident prevention and a decrease in their consequences. Importance of the checkability of the circuits for ensuring safety in critical applications is emphasized as safety is based on the use of fault tolerant circuitry decisions and their efficiency is defined by the circuit checkability. Development of a logical checkability from testability to structurally functional and dual-mode model which formalizes a problem of the hidden faults and defines ways of its solution is shown. The limitation of a logical checkability in detection of faults in chains of the common signals and the need for development of checkability out of the limits of a logical form, including suitability to checking the circuits on the basis of their power consumption is considered. Power-consumption-oriented checkability (Power-checkability) allowing detection of faults in chains of the common signals is defined. Its analytical assessment for the circuits implemented in FPGA is offered. Experiments providing estimation of power-checkability for FPGA-implementation of iterative array multipliers with various activities of input signals are carried out.

show abstract

Section: Related Work Goal and Structure Of The Papermentioning

confidence: 99%