2016
DOI: 10.1117/12.2221910
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SEM based overlay measurement between resist and buried patterns

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Cited by 6 publications
(4 citation statements)
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“…Figure 7 shows CD-SEM imaging for SRAM pattern after DD etching. 37 This layout has via-in-trench with large metal trench region. CD-SEM can measure overlay in SRAM region between V0 and M1 directly.…”
Section: Dedicated Mark and Algorithm Of Sem-ol Metrologymentioning
confidence: 99%
See 1 more Smart Citation
“…Figure 7 shows CD-SEM imaging for SRAM pattern after DD etching. 37 This layout has via-in-trench with large metal trench region. CD-SEM can measure overlay in SRAM region between V0 and M1 directly.…”
Section: Dedicated Mark and Algorithm Of Sem-ol Metrologymentioning
confidence: 99%
“…Then high-voltage SEM was developed to fulfill these requirements. 37,38 SEM-OL measurements made it possible to feedback to mask or scanner linear overlay 10 correctable terms. It was applied for improvement in R&D, Technology Ramp and for process monitor in manufacturing.…”
Section: Introductionmentioning
confidence: 99%
“…With the continuous shrink in pattern size and increased density, overlay and edge-placement [13][14][15][16][17] control has become one of the most critical issues in semiconductor manufacturing. In particular, there is a clear need for SEMbased overlay measurements of after develop inspection (ADI) wafers, to serve as reference for optical overlay and make the necessary corrections before etching.…”
Section: Sem-based Overlay Measurement Between Resist and Buried Patt...mentioning
confidence: 99%
“…In addition, the overall size of these targets is relatively small (2 × 2 μm or less), thus allowing their in-chip placement. 13,14) In Fig. 1, we report SEM-based overlay measurements obtained using high voltage SEM.…”
Section: Sem-based Overlay Measurement Between Resist and Buried Patt...mentioning
confidence: 99%