Semi-analytical modeling of high performance nano-scale complementary logic gates utilizing ballistic carbon nanotube transistors

Jooq, Mohammad Khaleqi Qaleh; Mir, Ali; Mirzakuchaki, Sattar; Farmani, Ali

doi:10.1016/j.physe.2018.08.008

Cited by 31 publications

(7 citation statements)

References 57 publications

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“…23 These obstacles have obliged the chip manufacturers to look forward to alternatives for the conventional CMOS technology. 24,25 Among the various solutions, FinFET with higher gate controllability, smaller subthreshold swing factor, and the ease of fabrication in commercial silicon manufacturing facilities has been introduced as a successful replacement for the conventional planar CMOS technology. 26 FinFETs can be established with common multigate (CMG) and IDG structures.…”

Section: Fundamental Platformmentioning

confidence: 99%

“…As the silicon industry has moved towards the nanometric regime, CMOS transistors have dealt with various critical short‐channel effects such as carrier mobility degradation, velocity saturation, random dopant fluctuations, and drain‐induced barrier lowering 23 . These obstacles have obliged the chip manufacturers to look forward to alternatives for the conventional CMOS technology 24,25 . Among the various solutions, FinFET with higher gate controllability, smaller subthreshold swing factor, and the ease of fabrication in commercial silicon manufacturing facilities has been introduced as a successful replacement for the conventional planar CMOS technology 26 .…”

Section: Introductionmentioning

confidence: 99%

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Ultra‐efficient fully programmable membership function generator based on independent double‐gate FinFET technology

Jooq

Behbahani

Moaiyeri

2023

Circuit Theory & Apps

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SummaryThis paper demonstrates an ultra‐efficient, fully programmable membership function generator (MFG) utilizing independent double‐gate (IDG) FinFET technology. The proposed MFG can produce s‐shaped, z‐shaped, triangular, and trapezoidal membership functions. By employing only six transistors, the designed MFG provides full controllability over the height, position, width, and slope of the generated waveforms. Without using any additional transistor and changing the dimensions, the proposed MFG can calibrate the slope of the output based on the back‐gate bias voltage of the IDG‐FinFETs. According to our extensive simulations, the proposed MFG shows promising improvements in transistor count (70%), power‐delay‐product (PDP) (80%), and maximum absolute error (61%) as compared with its state‐of‐the‐art counterparts. To benchmark the functionality of the proposed MFG in practical applications, our generated membership function is exploited as the neuron's activation function in a multilayer perceptron (MLP) neural network. The simulation results indicate that the training process of the simulated MLP with the proposed MFG closely tracks the results obtained from the ideal MLP with the sigmoid activation function. A figure of merit (FoM) is defined considering the hardware efficiency and accuracy of the neural networks to evaluate the entire performance of the proposed MFG. The FoM simulations demonstrate that the proposed MFG presents an excellent trade‐off between hardware performance and accuracy in neural network applications. Our results emphasize that the proposed MFG is a potential candidate for designing high‐performance on‐chip neural networks.

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Section: Fundamental Platformmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Ultra‐efficient fully programmable membership function generator based on independent double‐gate FinFET technology

Jooq

Behbahani

Moaiyeri

2023

Circuit Theory & Apps

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“…This drawback makes the design and predictive simulation of complex circuits ineffective. Some discrete models based on LUTs [25] and some semi-analytical models [26], [27]…”

Section: Devices Based On 2d -Materials For Analog Dnnsmentioning

confidence: 99%

Assessment of Two-Dimensional Materials-Based Technology for Analog Neural Networks

Paliy

Strangio

Ruiu

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Embedding advanced cognitive capabilities in batteryconstrained edge devices requires specialized hardware with new circuit architecture andin the medium/long term -new device technology. We evaluate the potential of recently investigated devices based on 2D materials for the realization of analog deep neural networks, by comparing the performance of neural networks based on the same circuit architecture using three different device technologies for transistors and analog memories. As a reference result, it is included in the comparison also an implementation on a standard 0.18 m CMOS technology. Our architecture of choice makes use of current-mode analog vector-matrix multipliers based on programmable current mirrors consisting of transistors and floating-gate non-volatile memories. We consider experimentally demonstrated transistors and memories based on a monolayer Molibdenum Disulfide channel and ideal devices based on heterostructures of multilayermonolayer PtSe2. Following a consistent methodology for device-circuit co-design and optimization, we estimate layout area, energy efficiency and throughput as a function of the equivalent number of bits (ENOB), which is strictly correlated to classification accuracy. System-level tradeoffs are apparent: for a small ENOB experimental MoS2 floating-gate devices are already very promising; in our comparison a larger ENOB (7 bits) is only achieved with CMOS, signaling the necessity to improve linearity and electrostatics of devices with 2D materials.

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“…According to the device structure, CNTFETs can be mainly divided into three categories: MOS-like CNTFETs, Schottky barrier (SB) CNTFETs and tunnelling CNTFETs [9]. In general, MOS-like CNTFETs have the advantages of higher on-current and lower off-current, higher transconductance (g m ), higher cut-off frequency (f T ) and lower parasitic capacitance than silicon-based CNTFETs [10,11]. To design CNT-FET based circuits, a compact model compatible with existing electronics design automation (EDA) platforms, e.g.…”

Section: Introductionmentioning

confidence: 99%

“…Overall, the structural factors are seldom considered in currently available compact models, although the capacitance numerical modelling using a finite-element method (FEM) of a wrapped gate CNTFET has been proposed by M Akanda [23]. In 2018, M K Q Jooq et al from Lorestan University proposed a semi-analytical model for GAA CNTFET computing applications, and did some work on logic gate simulation and power consumption calculation [11]. Actually, CNTFETs with a wrapped gate may have a better current transmission characteristic compared with top gate.…”

Section: Introductionmentioning

confidence: 99%

Modification of a carbon nanotube FET compact model for digital circuit simulation

Cheng¹,

Zhu²,

Wu³

et al. 2020

Semicond. Sci. Technol.

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Carbon nanotube field-effect transistor (CNTFET) based circuit systems ha ve received extensive attention due to their energy-efficiency benefits. However, there is not yet a generally accepted compact SPICE model for CNTFETs compatible with existing electronics design automation platforms. In this paper, the Stanford top gate CNTFET model is optimized through the consideration of different doping levels in source/drain as well as the simplification of an equivalent capacitance network in the intrinsic channel. Based on this, compact models are built for both top gate and wrapped gate CNTFETs. Then the DC properties and the cut-off frequency of top gate and wrapped gate CNTFETs with 15 nm channel length, and their basic logic circuits based on our modelling, are simulated by HSPICE. In the circuit simulation, we add the influence of gate-to-gate capacitance. The influences of structural parameters such as the diameter, number of CNTs and their gap on the current-voltage property, transconductance, cut-off frequency, circuit delay and power consumption are studied. Through comparison with the simulation using the Stanford model, our modelling is more suitable for the design and development of CNTFET circuits. For given parameters, the top gate CNTFETs have a larger maximum cut-off frequency and the wrapped gate CNTFETs' saturate current is larger. Wrapped gate logic circuits have less delay but more dynamic power than top gate circuits. More CNTs in FETs with a bigger gap and shorter tube pitch lead to less circuit delay and more dynamic power.

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Semi-analytical modeling of high performance nano-scale complementary logic gates utilizing ballistic carbon nanotube transistors

Cited by 31 publications

References 57 publications

Ultra‐efficient fully programmable membership function generator based on independent double‐gate FinFET technology

Ultra‐efficient fully programmable membership function generator based on independent double‐gate FinFET technology

Assessment of Two-Dimensional Materials-Based Technology for Analog Neural Networks

Modification of a carbon nanotube FET compact model for digital circuit simulation

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