Semi Analytical Modelling for Drain-Induced Barrier Lowering Reduction in Dual-Metal Gate all Around FET

Abstract

In the research paper, the semi-analytical modelling is done for low drain-induced barrier lowering (DIBL) dual-metal gate all around FET (DM GAAFET). Vacuum and silicon nitride are considered in the act of the gate oxide material near drain region for dual-metal vacuum oxide gate all around FET (DM-VO GAAFET) and dual-metal nitride oxide gate all around FET (DM-NO GAAFET) respectively, in which surface potential, threshold voltage, and DIBL are modelled for both the devices. The proposed models are validated by comparing DM-NO GAAFET with DM-VO GAAFET. DM-NO GAAFET shows the better device performance than DM-VO GAAFET as the threshold voltage increased by 10% and DIBL decreased by 50% in simulated as well as analytical results. The obtained results are having very close agreement with simulated results for both the GAAFETs.