Semi-classical noise investigation for sub-40nm metal-oxide-semiconductor field-effect transistors

Abstract

Device white noise levels in short channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) dictate the performance and reliability of high-frequency circuits ranging from high-speed microprocessors to Low-Noise Amplifiers (LNAs) and microwave circuits. Recent experimental noise measurements with very short devices demonstrate the existence of suppressed shot noise, contrary to the predictions of classical channel thermal noise models. In this work we show that, as the dimensions continue to shrink, shot noise has to be considered when the channel resistance becomes comparable to the barrier resistance at the source-channel junction. By adopting a semi-classical approach and taking retrospectively into account transport, short-channel and quantum effects, we investigate the partitioning between shot and thermal noise, and formulate a predictive model that describes the noise characteristics of modern devices.

Physics-Informed Neural Network for High Frequency Noise Performance in Quasi-Ballistic MOSFETs

“…This is generated by the positive correlation between tunneling into the gate due to the interplay between the DOS and electrostatics [15,23]. For moderately high voltages in the inversion region, as can be seen in Figure 5b, f R is so low that injection noise from the left reservoir is dominant, leading to the noise suppression (Γ d < 1) in the drain shot noise [1,[14][15][16][17][18]. This observation suggests that at T = 300 K, the major noise source shifts from thermal noise to shot noise.…”

“…The HF noise sources in MOSFETs include the thermal drain current noise, due to the channel resistance, giving rise to the induced gate noise and the correlation noise [2][3][4][5][6][7]. In the quasi-ballistic regime, with the channel length comparable to the mean free path length of carriers, there is a tunneling current and its shot noise through the source-todrain (SD) potential barrier [8][9][10][11][12][13][14][15][16][17][18]. Moreover, the continuous reduction of gate oxide thickness leads to tremendous gate tunneling currents and noise [2,[19][20][21][22][23][24].…”

Unified Model of Shot Noise in the Tunneling Current in Sub-10 nm MOSFETs

“…Advances in nanofabrication technology have opened up the possibility of surpassing the ultimate performance limits of modern CMOS devices [1,2]. However, the sub-10 nm channel length in MOSFETs gives rise to tunneling current and associated shot noise through the source-to-drain (SD) potential barrier [3][4][5][6][7][8][9][10][11][12][13][14][15]. With the downscaling of device dimensions, the continuous reduction in gate oxide thickness leads to enormous gate tunneling currents and noise [16][17][18][19][20][21][22][23].…”

“…These factors set fundamental limits on future CMOS technologies, because significant tunneling currents and shot noise are expected under normal operating conditions. The intriguing properties of shot noise, which have been extensively studied in mesoscopic devices, should manifest themselves in sub-10 nm MOSFETs, as the devices enter the ballistic transport regime [9][10][11][12][13][14][15]. However, analytical and highly predictive noise models in ballistic MOSFETs for circuitlevel simulation are still lacking [10][11][12].…”

“…However, analytical and highly predictive noise models in ballistic MOSFETs for circuitlevel simulation are still lacking [10][11][12]. Although the need for a unified model of shot noise in the SD and gate tunneling current arises frequently in quasi-ballistic MOSFET operation, these currents are typically treated separately for each case [9][10][11][12][13][14][15][21][22][23]. In this work, a single unified analytical expression is presented for the SD and gate tunneling currents and the associated shot noise, emphasizing their similarities and differences.…”