Proceedings of the 2007 International Symposium on Physical Design 2007
DOI: 10.1145/1231996.1232025
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Semi-detailed bus routing with variation reduction

Abstract: A bus routing algorithm is presented which not only minimizes wire length but also selects the bits in the bus to avoid twisting and conflicts. The resulting bus routes are regular, thus having strong immunity to variations. Minimization for wire length/delay differences between different bits is also implemented.

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Cited by 10 publications
(14 citation statements)
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“…Various bus routing algorithms [11,3,9] including ours can be plugged in to the floorplanner to handle buses. The cost function used in the simulated annealing was…”
Section: Resultsmentioning
confidence: 99%
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“…Various bus routing algorithms [11,3,9] including ours can be plugged in to the floorplanner to handle buses. The cost function used in the simulated annealing was…”
Section: Resultsmentioning
confidence: 99%
“…A type of interlocking, two turning nodes being connected by a short edge, was discussed in [9]. The concept of interlocking will be extended in the next definition.…”
Section: Terminologies and Problem Formulationmentioning
confidence: 99%
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