Semi-Iterative Analog Turbo Decoding

Abstract

This paper presents a novel analog turbo decoding architecture allowing analog decoders for long frame lengths to be implemented on a single chip. This is made possible by suitably using slicing techniques which allow hardware reuse and re-configurability. The architecture is applied to a DVB-RCS-like code. It shows a reduction of occupied chip area by a factor of ten when compared to a conventional slice design with no significant performance degradation. A single 27mm² 0.25µm BiCMOS decoder can then decode any frame length from 40 up to 1824 bits.I.

20 Years of Turbo Coding and Energy-Aware Design Guidelines for Energy-Constrained Wireless Applications

“…Furthermore, accurately simulating the BER performance of the circuit before its fabrication is not feasible or accurate. In [58] an analog architecture, which supports long frames is described, although this is associated with other challenges. In particular, a sampling circuit is required at each input of the decoder, which holds the analog value constant during decoding.…”

Current-mode memory cell with power down phase for discrete time analog iterative decoders

“…For analog iterative decoders, where data processing is parallel and thousands of bits are evaluated at the same time (see e.g. [8]), thousands of analog memory elements are needed. Thus there is a strong demand for a high speed, ultra low power elements with simple structures to minimize overall power dissipation and chip area.…”

“…In this paper we propose a sampling circuit for an analog iterative decoder structure based on discrete-time processing of log-likelihood messages (a decoder architecture proposed in [8]), shown conceptually in Fig. 1.…”