Semiformal Assertion-Based Verification of Hardware/Software Systems in a Model-Driven Design Framework

Pravadelli, Graziano; Quaglia, Davide; Vinco, Sara; Fummi, Franco

doi:10.1007/978-94-017-7267-9_23

Handbook of Hardware/Software Codesign 2017

DOI: 10.1007/978-94-017-7267-9_23

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Semiformal Assertion-Based Verification of Hardware/Software Systems in a Model-Driven Design Framework

Graziano Pravadelli¹,

Davide Quaglia²,

Sara Vinco³

et al.

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2019

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A Cross-level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors

Vinco

Bombieri

Pagliari

et al. 2019

ACM Trans. Des. Autom. Electron. Syst.

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Smart systems are characterized by the integration in a single device of multi-domain subsystems of different technological domains, namely, analog, digital, discrete and power devices, MEMS, and power sources. Such challenges, emerging from the heterogeneous nature of the whole system, combined with the traditional challenges of digital design, directly impact on performance and on propagation delay of digital components. This article proposes a design approach to enhance the RTL model of a given digital component for the integration in smart systems with the automatic insertion of delay sensors, which can detect and correct timing failures. The article then proposes a methodology to verify such added features at system level. The augmented model is abstracted to SystemC TLM, which is automatically injected with mutants (i.e., code mutations) to emulate delays and timing failures. The resulting TLM model is finally simulated to identify timing failures and to verify the correctness of the inserted delay monitors. Experimental results demonstrate the applicability of the proposed design and verification methodology, thanks to an efficient sensor-aware abstraction methodology, by applying the flow to three complex case studies.

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A Cross-level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors

Vinco

Bombieri

Pagliari

et al. 2019

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

show abstract

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Semiformal Assertion-Based Verification of Hardware/Software Systems in a Model-Driven Design Framework

Cited by 1 publication

References 53 publications

A Cross-level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors

A Cross-level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors

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