Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm

Patel, Dhruv; Wright, Derek; Sachdev, Manoj

doi:10.1109/ets.2018.8400696

2018 IEEE 23rd European Test Symposium (ETS) 2018

DOI: 10.1109/ets.2018.8400696

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Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm

Dhruv Patel

Derek Wright

Manoj Sachdev

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2024

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Real‐time bit‐line leakage balance circuit with four‐input low‐offset SA considering threshold voltage for SRAM stability design

Peng,

Hu,

Zheng

et al. 2024

Circuit Theory & Apps

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In an SRAM, threshold voltages of transistors decrease as the CMOS process technology scales down into the nanometer scale, which causes the leakage currents on the bit‐lines. The bit‐line leakage current slows reading operations or even causes reading errors. In this paper, we proposed a new scheme called RTB, which is combined with a four‐input low‐offset sense amplifier with threshold voltage consideration to solve the problem caused by bit‐line leakage current. This scheme adopts 8T cells and two pairs of bit‐lines connected to a four‐input sense amplifier to balance the bit‐line leakage current in real‐time. In this way, the maximum tolerable bit‐line leakage current can be effectively increased and the reading operation can be accelerated. Simulations in the 55 nm CMOS process design kits under different process corners, temperatures, and voltages show that the proposed scheme can increase the maximum tolerable leakage to more than 300 μA.

show abstract

Real‐time bit‐line leakage balance circuit with four‐input low‐offset SA considering threshold voltage for SRAM stability design

Peng,

Hu,

Zheng

et al. 2024

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

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Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm

Cited by 1 publication

References 18 publications

Real‐time bit‐line leakage balance circuit with four‐input low‐offset SA considering threshold voltage for SRAM stability design

Real‐time bit‐line leakage balance circuit with four‐input low‐offset SA considering threshold voltage for SRAM stability design

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