The number of bits required to accurately represent a received signal in a wireless system changes as the out-of-band interference is removed by an IIR digital filter, if the fdtering is done in stages, such as second-order sections. Taking advantage of this fact can reduce the size of the datapath in a VLSI realization of a digital fdter, and hence power and area can be saved without decreasing performance. An effective algorithm for computing this reduced number of bits to use for quantization after each stage is derived, and a scheme for optimally ordering the second-order sections is presented. Power savings range from 33% to 50%, depending on the amount of out-ofband interference.