Sensitization criterion for threshold logic circuits and its application

Abstract

Threshold logic has been known as an alternative representation of Boolean logic due to its compactness characteristic. Recently, the developments in advanced nanotechnologies have also promised efficient implementations of threshold logic gates. Thus, many synthesis methodologies for threshold logic circuits have been proposed. Since threshold logic has a different mechanism in functional evaluation compared to the traditional Boolean logic, a threshold logic gate can represent a more complex function. As a result, the sensitization criterion in threshold logic circuits is also different. In this work, we propose a sensitization criterion for threshold logic circuits, and show its application to the static timing analysis problem. The experimental results show the accuracy of the proposed criterion.

Width minimization in the Single-Electron Transistor array synthesis

“…, w n ; T to represent an LTG. We also transform the negative weights of an LTG into positive ones by applying a Positive-Negative weight transformation procedure [12][14] [18] for ease of analysis in this work.…”