Sensor-Based Approximate Adder Design for Accelerating Error-Tolerant and Deep-Learning Applications

Huang, Ning-Chi; Chen, Szu-Ying; Wu, Kai–Chiang

doi:10.23919/date.2019.8714949

Cited by 11 publications

(4 citation statements)

References 15 publications

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“…Adder contributes to the whole system's performance and influences the total energy consumption. Thus, introducing the inexactness in the addition process curtails the power, area, and delay while improving the whole system's performance [ 8 , 9 ].…”

Section: Convolutional Neural Network Accelerator For the Handwritten...mentioning

confidence: 99%

“…In this work, an accelerator to accelerate the CNN for handwritten digit classification application is developed through dedicated fixed-point approximate arithmetic blocks for the convolution operation. A similar kind of accelerator work can be found in the literature, but for accelerating softmax regression [ 8 ] and image to column operation [ 9 ] alone.…”

Section: Convolutional Neural Network Accelerator For the Handwritten...mentioning

confidence: 99%

“…Other similar types of inexact adders such as Significance Approximation Error-Tolerant Carry Select Adder (SAET-CSLA) based on Approximate Full Adder (AFA) [ 5 ], Modified Full Adder- (MFA-) based High-Speed Error-Tolerant Adder (HSETA) [ 6 ], and MUX-based High-Performance Error-Tolerant Adder (HPETA) [ 7 ] are designed, and better performance is demonstrated with image blending applications. Carry Truncate Adder (CTA) [ 8 ] is deployed in Convolution Neural Network (CNN) structure for accelerating the computation of the softmax layer. Generic Accuracy Configurable Adder (GeAr) is modified and implemented in the CNN-based Caffe network to accelerate the image to column conversion process [ 9 ].…”

Section: Introductionmentioning

confidence: 99%

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Power and Area Efficient Cascaded Effectless GDI Approximate Adder for Accelerating Multimedia Applications Using Deep Learning Model

Nagarajan

Muthaiah

Teekaraman

et al. 2022

Computational Intelligence and Neuroscience

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Approximate computing is an upsurging technique to accelerate the process through less computational effort while keeping admissible accuracy of error-tolerant applications such as multimedia and deep learning. Inheritance properties of the deep learning process aid the designer to abridge the circuitry and also to increase the computation speed at the cost of the accuracy of results. High computational complexity and low-power requirement of portable devices in the dark silicon era sought suitable alternate for Complementary Metal Oxide Semiconductor (CMOS) technology. Gate Diffusion Input (GDI) logic is one of the prompting alternatives to CMOS logic to reduce transistors and low-power design. In this work, a novel energy and area efficient 1-bit GDI-based full swing Energy and Area efficient Full Adder (EAFA) with minimum error distance is proposed. The proposed architecture was constructed to mitigate the cascaded effect problem in GDI-based circuits. It is proved by extending the proposed 1-bit GDI-based adder for different 16-bit Energy and Area Efficient High-Speed Error-Tolerant Adders (EAHSETA) segmented as accurate and inaccurate adder circuits. The proposed adder’s design metrics in terms of delay, area, and power dissipation are verified through simulation using the Cadence tool. The proposed logic is deployed to accelerate the convolution process in the Low-Weight Digit Detector neural network for real-time handwritten digit classification application as a case study in the Intel Cyclone IV Field Programmable Gate Array (FPGA). The results confirm that our proposed EAHSETA occupies fewer logic elements and improves operation speed with the speed-up factor of 1.29 than other similar techniques while producing 95% of classification accuracy.

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Section: Convolutional Neural Network Accelerator For the Handwritten...mentioning

confidence: 99%

Section: Convolutional Neural Network Accelerator For the Handwritten...mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Power and Area Efficient Cascaded Effectless GDI Approximate Adder for Accelerating Multimedia Applications Using Deep Learning Model

Nagarajan

Muthaiah

Teekaraman

et al. 2022

Computational Intelligence and Neuroscience

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show abstract

“…Computationally intensive applications, such as image processing, machine learning, and data mining, may have inherent error tolerance, and a certain amount of computation error is acceptable in these applications [2,3,4,5,6]. Therefore, the design of efficient approximate adders that reduce power and energy has drawn great attention, and a large number of approximate adders have been proposed in the recent years [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29]. The lower-part OR adder (LOA) divides an adder into two: accurate and inaccurate parts [7].…”

Section: Introductionmentioning

confidence: 99%

Approximate adder design with simplified lower-part approximation

Lee

Seo

Kim

et al. 2020

IEICE Electron. Express

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This letter presents a novel approximate adder that reduces energy and power consumption by leveraging a simplified lower-part approximation. The proposed scheme reduces hardware costs while providing an acceptable accuracy performance. Implemented in a 32-CMOS technology, the proposed adder achieves area and power reductions of 67% and 91%, respectively, compare to a conventional adder. In terms of energy, it improves the power-delay and energy-delay products by 13.1% and 17.0%, respectively, compared to the other approximate adders considered herein. In addition, when adopted in a digital image processing application, the proposed adder shows a very promising output quality compared to that produced by an exact adder while providing excellent energy efficiency.

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Multi-modal interaction using time division long-term evolution (TD-LTE) for space designing exhibition

Yang

2023

Wireless Netw

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Sensor-Based Approximate Adder Design for Accelerating Error-Tolerant and Deep-Learning Applications

Cited by 11 publications

References 15 publications

Power and Area Efficient Cascaded Effectless GDI Approximate Adder for Accelerating Multimedia Applications Using Deep Learning Model

Power and Area Efficient Cascaded Effectless GDI Approximate Adder for Accelerating Multimedia Applications Using Deep Learning Model

Approximate adder design with simplified lower-part approximation

Multi-modal interaction using time division long-term evolution (TD-LTE) for space designing exhibition

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