Sequential Element Design With Built-In Soft Error Resilience

Zhang, Ming; Mitra, Subhasish; Mak, T.M.; Seifert, N.; Wang, N.J.; Shi, Qi; Kim, Kee Sup; Shanbhag, Naresh R.; Patel, Sanjay J.

doi:10.1109/tvlsi.2006.887832

Cited by 179 publications

(68 citation statements)

References 33 publications

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“…The most prominent techniques include TMR, BISER, Razor, GRAAL, Razor II and information redundancy [5,6,7,8,9,14]. TMR and BISER techniques employ hardware redundancy to mask hard errors and/or SEU at latch and flip-flop outputs.…”

Section: A Fault-tolerance In Logic Circuitsmentioning

confidence: 99%

“…These circuits are combined of combinational logic and sequential elements such as latches and flip-flops. Different techniques have been proposed to protect the sequential part from hard errors and/or SEUs [5,6,7,8,9]. Some of these techniques are also efficient for SETs and timing errors that arrived at the combinational part of logic circuits [7,8].…”

Section: Introductionmentioning

confidence: 99%

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A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

et al. 2014

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This paper presents a new hybrid fault-tolerant architecture for robustness improvement of digital CMOS circuits and systems. It targets all kinds of errors in combinational part of logic circuits and thus, can be combined with advanced SEU protection techniques for sequential elements while reducing the power consumption. The proposed architecture combines different types of redundancies: information redundancy for error detection, temporal redundancy for soft error correction and hardware redundancy for hard error correction. Moreover, it uses a pseudo-dynamic comparator for SET and timing errors detection. Besides, the proposed method also aims to reduce power consumption of fault-tolerant architectures while keeping a comparable area overhead compared to existing solutions. Results on the largest ISCAS'85 and ITC'99 benchmark circuits show that our approach has an area cost of about 3% to 6% with a power consumption saving of about 33% compared to TMR architectures. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by Springer Science+Business Media New York.

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Section: A Fault-tolerance In Logic Circuitsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

et al. 2014

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“…Garg et al [10] supplemented the duplication by connecting the outputs of the gates by a diode or a transistor. There are also techniques to harden the flip-flops of the circuit, or a subset of its flip-flops [16], [24], [38].…”

Section: Selective Hardeningmentioning

confidence: 99%

“…There could also be some optimization potential from sharing the duplicated logic. Using BISER [38] as the hardening mechanism for a flip-flop would lead to little area but significant energy overhead. An accurate model of hardening costs c i is not in the scope of this paper.…”

Section: Selective Hardening Mechanismmentioning

confidence: 99%

Modeling and Mitigating Transient Errors in Logic Circuits

Polian

Hayes

Reddy

et al. 2011

IEEE Trans. Dependable and Secure Comput.

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Abstract-Transient or soft errors caused by various environmental effects are a growing concern in micro and nanoelectronics. We present a general framework for modeling and mitigating the logical effects of such errors in digital circuits. We observe that some errors have time-bounded effects; the system's output is corrupted for a few clock cycles, after which it recovers automatically. Since such erroneous behavior can be tolerated by some applications, i.e., it is noncritical at the system level, we define the critical soft error rate (CSER) as a more realistic alternative to the conventional SER measure. A simplified technology-independent fault model, the single transient fault (STF), is proposed for efficiently estimating the error probabilities associated with individual nodes in both combinational and sequential logic. STFs can be used to compute various other useful metrics for the faults and errors of interest, and the required computations can leverage the large body of existing methods and tools designed for (permanent) stuck-at faults. As an application of the proposed methodology, we introduce a systematic strategy for hardening logic circuits against transient faults. The goal is to achieve a desired level of CSER at minimum cost by selecting a subset of nodes for hardening against STFs. Exact and approximate algorithms to solve the node selection problem are presented. The effectiveness of this approach is demonstrated by experiments with the ISCAS-85 and -89 benchmark suites, as well as some large (multimillion-gate) industrial circuits.

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“…However, these techniques tend to increase power consumption and lower the speed of the circuit. Logic level solutions [58], [59], [60] mainly propose detection and recovery in combinational circuits by using redundant or selfchecking circuits. Architectural solutions mainly introduce redundant hardware in the system to make the whole system more robust against soft errors.…”

Section: Related Workmentioning

confidence: 99%