Sequential equivalence checking of clock-gated circuits

Abstract

We review some general theorems, proved in a previous paper, about situations

Verification and Synthesis of Clock-Gated Circuits

“…Section 2.5 summarizes the results and discusses some limitations of the proposed method. 1 The full version of this chapter has been published in Design Automation Conference 2015 [12].…”

“…Those sufficient conditions of legal clock-gating are formulated using CGs and then proved on the original circuits. Here we only demonstrate standard examples for this thesis, while the proposed theorems and algorithms, as well as proofs are detailed in [12].…”

“…To verify if the clock-gating condition on F 5 and F 6 is legal, i.e. the connection from F 1 to the MUXes is sequentially redundant, a sufficient condition proposed by the CG method (detailed in [12]) is that both the following conditions are satisfied:…”

“…Given a set of properties P, multiP rove(P) verifies all properties simultaneously, and then returns the resulting set proof, which lists both proved and disproved properties. At Line 13, isLegal(proof) analyzes the result and determines if candidate is sequentially redundant using theorems stated in [12]. When any of the sufficient conditions proposed by the theorems is satisfied, the candidate is proved.…”

“…The second set of experiments compares the scalability of the three above methods by applying them to the same design (qmult taken from OpenCores [33]), but with varying bit-widths (8)(9)(10)(11)(12)(13)(14)(15)(16). As the widths increase, the combinational part gets more complex.…”