2008 9th International Conference on Ultimate Integration of Silicon 2008
DOI: 10.1109/ulis.2008.4527170
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Series resistance in vertical MOSFETs with reduced drain/source overlap capacitance

Abstract: In this work we investigate the series resistances in vertical MOSFETs incorporating the fillet local oxidation (FILOX) structure that serves to reduce the gate to drain/source overlap capacitances. The series resistances are modeled analytically and the important influencing factors, namely gate bias dependence and the asymmetric nature of the device, are identified. We extract by simulation, R d and R s from devices with different FILOX thicknesses, employing an impedance method often used in RF characterisa… Show more

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Cited by 1 publication
(2 citation statements)
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“…The 6.5 times difference in I on between the measurement and simulation at V GS =1.5V, indicates that the intrinsic resistance of the fabricated device has an approximate value of 1590 Ω·μm. This value is similar to that predicted by the analytical model and also values extracted from a numerical model using an RF technique [8]. A lower intrinsic resistance could be obtained using a higher RTA thermal budget to diffuse the junctions beyond the region of FILOX encroachment.…”
Section: Ekv Modellingsupporting
confidence: 85%
See 1 more Smart Citation
“…The 6.5 times difference in I on between the measurement and simulation at V GS =1.5V, indicates that the intrinsic resistance of the fabricated device has an approximate value of 1590 Ω·μm. This value is similar to that predicted by the analytical model and also values extracted from a numerical model using an RF technique [8]. A lower intrinsic resistance could be obtained using a higher RTA thermal budget to diffuse the junctions beyond the region of FILOX encroachment.…”
Section: Ekv Modellingsupporting
confidence: 85%
“…However, the frame gate also causes an increase to the gate to drain/source overlap area which can in turn degrade the peak f T up to 2.2 times compared to the DG device as shown by the measurements illustrated in Fig 9 (left axis). In Fig 9 (right axis), the fmax of FGC and DGC device are evaluated using f T source resistance R s [8], gate-to-drain parasitic capacitance Cgd and output admittance g ds values from the optimised/calibrated numerical model and aforementioned measured Rg. Note that the f T difference of the two structures is taken into account with reference to the difference between measured values.…”
Section: Ekv Modellingmentioning
confidence: 99%