SESAM: An MPSoC Simulation Environment for Dynamic Application Processing

Ventroux, Nicolas; Guerre, Alexandre; Sassolas, Tanguy; Moutaoukil, L.; Blanc, G.; Bechara, Charly; David, Raphaël

doi:10.1109/cit.2010.322

Cited by 25 publications

(7 citation statements)

References 10 publications

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“…These metrics would give information about the absorption capacities of access requests. That is why we plan to use a microarchitecture simulation environment such as [29] for evaluating time performances of our proposed strategy. We also aim to use a scalable cache coherent NUMA architecture such as [30] that allows us to implement our proposal in a highly parallel platform.…”

Section: Discussionmentioning

confidence: 99%

Introducing a Data Sliding Mechanism for Cooperative Caching in Manycore Architectures

Dahmani

Cudennec

Gogniat

2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

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In future micro-architectures, the increase of the number of cores and wire network complexity is leading to several performance degradation. These platforms are intended to process large amount of data. One of the biggest challenges for systems scalability is actually the memory wall: the memory latency is hardly increasing compared to technology expectations. Recent works explore potential software and hardware solutions mainly based on different caching schemes for addressing off-chip access issues.In this paper, we propose a new cooperative caching method improving the cache miss rate for manycore micro-architectures. The work is motivated by some limitations of recent adaptive cooperative caching proposals. Elastic Cooperative caching (ECC), is a dynamic memory partitioning mechanism that allows sharing cache across cooperative nodes according to the application behavior. However, it is mainly limited with cache eviction rate in case of highly stressed neighborhood. Another system, the adaptive Set-Granular Cooperative Caching (ASCC), is based on finer set-based mechanisms for a better adaptability. However, heavy localized cache loads are not efficiently managed. In such a context, we propose a cooperative caching strategy that consists in sliding data through closer neighbors. When a cache receives a storing request of a neighbor's private block, it spills the least recently used private data to a close neighbor. Thus, solicited saturated nodes slide local blocks to their respective neighbors to always provide free cache space. We also propose a new Prioritybased Data Replacement policy to decide efficiently which blocks should be spilled, and a new mechanism to choose host destination called Best Neighbor selector.The first analytic performance evaluation shows that the proposed cache management policies reduce by half the average global communication rate. As frequent accesses are focused in the neighboring zones, it efficiently improves on-Chip traffic.Finally, our evaluation shows that cache miss rate is enhanced: each tile keeps the most frequently accessed data 1-Hop close to it, instead of ejecting them Off-Chip. Proposed techniques notably reduce the cache miss rate in case of high solicitation of the cooperative zone, as it is shown in the performed experiments.

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Section: Discussionmentioning

confidence: 99%

Introducing a Data Sliding Mechanism for Cooperative Caching in Manycore Architectures

Dahmani

Cudennec

Gogniat

2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

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“…Detailed CPU models with full pipelining description can be simulated at 0.1 Million Instructions Per Second (MIPS), whereas instruction-accurate CPU models can reach 1 MIPS. Other MPSoC modeling environments, such as SESAM [24] or Unisim [3] used instruction-based ISS generation librairies to support the modeling of various CPUs, reaching approximately 10 MIPS. However, this accuracy and ISA flexibility come at the cost of limited simulation speed, which hampers their capacity to address complex systems embedding several CPUs and running full-fledged OSes.…”

Section: Related Workmentioning

confidence: 99%

Fast Virtual Prototyping for Embedded Computing Systems Design and Exploration

Charif

Busnot

Mameesh

et al. 2019

Proceedings of the Rapid Simulation and Performance Evaluation: Methods and Tools

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Virtual Prototyping has been widely adopted as a costeffective solution for early hardware and software co-validation. However, as systems grow in complexity and scale, both the time required to get to a correct virtual prototype, and the time required to run real software on it can quickly become unmanageable. This paper introduces a feature-rich integrated virtual prototyping solution, designed to meet industrial needs not only in terms of performance, but also in terms of ease, rapidity and automation of modelling and exploration. It introduces novel methods to leverage the QEMU dynamic binary translator and the abstraction levels offered by SystemC/TLM 2.0 to provide the best possible trade-offs between accuracy and performance at all steps of the design. The solution also ships with a dynamic platform composition infrastructure that makes it possible to model and explore a myriad of architectures using a compact high-level description. Results obtained simulating a RISC-V SMP architecture running the PARSEC benchmark suite reveal that simulation speed can range from 30 MIPS in accurate simulation mode to 220 MIPS in fast functional validation mode.

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“…Manycore architecture simulator: The fast simulation phase is based on a Timed TLM simulator designed in the laboratory called SESAM [2] that delivers reports and statistics on some functional and non-functional criteria such as performance, power and reliability. The SESAM simulator will take as input the generated TLM top netlist, the TLM IP library, the generated SW runtime, and the compiled application to launch a global simulation.…”

Section: Figure 1 the Unified Ip-xact Based Design Flow For Fast Desimentioning

confidence: 99%

Towards an Automatic Co-generator for Manycores’ Architecture and Runtime: STHORM case-study

Bechara

Chehida

Thabet

2015

Procedia Computer Science

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SESAM: An MPSoC Simulation Environment for Dynamic Application Processing

Cited by 25 publications

References 10 publications

Introducing a Data Sliding Mechanism for Cooperative Caching in Manycore Architectures

Introducing a Data Sliding Mechanism for Cooperative Caching in Manycore Architectures

Fast Virtual Prototyping for Embedded Computing Systems Design and Exploration

Towards an Automatic Co-generator for Manycores’ Architecture and Runtime: STHORM case-study

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