SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects

Abstract

This paper presents a measurement circuit structure for capturing SET pulse-width suppressing pulse-width modulation and within-die process variation effects. For mitigating pulse-width modulation while maintaining area efficiency, the proposed circuit uses massively parallelized short inverter chains as a target circuit. Moreover, for each inverter chain on each die, pulse-width calibration is performed. In measurements, narrow SET pulses ranging 5 ps to 215 ps were obtained. We confirm that an overestimation of pulse-width may happen when ignoring die-to-die and within-die variation of the measurement circuit. Our evaluation results thus point out that calibration for within-die variation in addition to die-to-die variation of the measurement circuit is indispensable. key words: soft error, single event transient (SET), pulse-width, pulsewidth modulation, measurement circuit, within-die process variation Ryo Harada (S'09) received the B.E. and M.E. degrees in Information Systems Engineering from Osaka University, Osaka, Japan, in 2009. He is currently pursuing the Ph.D. degree in the Department of Information Systems Engineering at Osaka University. His research interests include soft error estiomation. Yukio Mitsuyama received B.E., M.E., and Ph.D. degrees in Information Systems Engineering from Osaka University, Japan, in 1998, 2000, and 2010, respectively. He is currently an Associate Professor in School of Engineering, Kochi University of Technology. His research interests include reconfigurable architecture and its VLSI design. He is a member of IEEE and IPSJ. sity. His research interest includes computeraided design for digital integrated circuits, and high speed and low power circuit design. Dr. Hashimoto served on the technical program committees for international conferences including DAC, ICCAD, ITC, Symposium on VLSI Circuits, ASP-DAC, DATE, and ISPD. He is a member of IEEE, ACM and IPSJ. Takao Onoye received the B.E. and M.E. degrees in Electronic Engineering, and Dr.Eng. degree in Information Systems Engineering all from Osaka University, Japan, in 1991Japan, in , 1993Japan, in , and 1997. He is currently a professor in the Department of Information Systems Engineering, Osaka University. His research interests include media-centric low-power architecture and its SoC implementation. He is a member of IEEE, IPSJ, and ITE-J.

An analytic evaluation on soft error immunity enhancement due to temporal triplication

“…For example, reference (Harada, 2014) shows that SET rate is lower than 1/100 of SEU rate in a 36 mm 2 chip, where SRAM and FFs occupy 1/2 and 1.4 of the chip, respectively. It should be noted that this rate comparison in (Harada, 2014) is based on (Harada et al, 2012(Harada et al, , 2014. Therefore, failures due to SEU have a stronger impact than failures due to SET in actual environment.…”