Settling time optimization technique for binary-weighted digital-to-analog converter

Kim, Hyo‐Jong; Seo, Donghwan; Lee, Byung-Geun

doi:10.1587/elex.11.20140132

IEICE Electron. Express

2014

DOI: 10.1587/elex.11.20140132

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Settling time optimization technique for binary-weighted digital-to-analog converter

Hyo‐Jong Kim

Donghwan Seo

Byung-Geun Lee

Abstract: Settling behavior of the binary-weighted switched-capacitor digital-to-analog converter output is analyzed and a design method for fast settling is presented. A calibration circuit that effectively reduces settling time beyond the process limit is also proposed and verified with various simulations.

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Design of binary weighted DAC for asynchronous ADC with improved slew rate and with calibrated size of capacitors

Ling¹,

Ikbal²

2020

J. vibroeng.

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This work proposed a binary-weighted Digital-to-Analog Converter (DAC), which is designed to be used in Asynchronous successive approximation register (SAR) based Analog-to-digital converters (ADCs) specifically and in other relevant operations .The design has yielded an improved slew rate, and it is less prone to noise as the size of capacitors is taken in accordance with KT/C noise calculation. For achieving all mentioned goals, and to restrict the size of DAC, within suitable dimensions charge scaling DACs are used. One more advantage of this design is its accuracy, further it does not require op-Amps for its operation. Results of statistical simulation and mathematical consideration are published which depicts the supremacy of the design. A high-resolution DAC designed for this specific purpose has to have special consideration for the effect of local mismatch, parasitic and matching of the capacitors, for that, the common-centroid approach has been followed. This design has displayed a high resolution with small unit capacitances and that too without expensive factory calibration.

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Design of binary weighted DAC for asynchronous ADC with improved slew rate and with calibrated size of capacitors

Ling¹,

Ikbal²

2020

J. vibroeng.

View full text Add to dashboard Cite

show abstract

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Settling time optimization technique for binary-weighted digital-to-analog converter

Cited by 1 publication

References 3 publications

Design of binary weighted DAC for asynchronous ADC with improved slew rate and with calibrated size of capacitors

Design of binary weighted DAC for asynchronous ADC with improved slew rate and with calibrated size of capacitors

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