SEU hardened layout design for SRAM cells based on SEU reversal

Abstract

In this paper, the generation mechanism of single event upset reversal (SEUR) between 2 PMOS in SRAM cells is studied in depth based on 45 nm CMOS technology. We find that SEUR not only depends on the charge sharing but also follows the rule that the charge collection of passive device is larger and longer than that of active device. Based on SEUR generation mechanism, two novel layouts named Drain-Source-Drain (DSD) and Dummy are proposed to increase the rate of SEUR for reducing SEU vulnerability of SRAM cells. Compared with the traditional layout, DSD and Dummy layout reduce 4.26% and 31.56% SEU sensitive area under normal incident, respectively. For tilted incident, Dummy layout sharply increases SEUR rate while DSD layout is not better than the traditional layout on enhancing SEUR. Consequently, the proposed Dummy layout can improve SEU reliability without area penalty.

Assessing alpha-particle-induced SEU sensitivity of flip-chip bonded SRAM using high energy irradiation

“…SRAM is the most susceptible electronic device to the ionization radiation. To reduce its vulnerability against radiation, many radiationhardened and tolerant memory cells' designs have been proposed, like [2,3]. Advanced memory devices are packaged upside down to achieve high-density packaging and for heat dissipation mitigation.…”