SEU Mitigation for SRAM Based on Dual Redundancy Check Method

Abstract

The application of Static Random-Access Memory (SRAM), becomes more and more widely in aviation. However, the large amount of SRAM cells is very vulnerable to radiation included single-event upset (SEU). Based on the detection requirement of SRAM's SEU, the detected circuit of the SEU on SRAM is designed. Then the method of redundancy check is used in the reinforcement of the SEU. The test results shows that the detection circuit can detect the SRAM-type storage chip sensitive bit of the single particle and the proposed method can improved the performance of anti-single particles of SRAM several times as high as 1E6.

An Improved Frame Level Redundancy Scrubbing Algorithm for SRAM based FPGA

“…Authors in [17] proposed a novel hybrid configuration scrubbing for the Xilinx 7-Series FPGAs by exploiting the onchip frame Error Correction Code (ECC). A dedicated nonconfigurable logic is built into the FPGA to compute a check word for each frame during configuration readback process for single bit error detection where the internal ECC circuitry computes the location of the error and corrects the upset.…”