SEU sensitivity of Junctionless Single-Gate SOI MOSFETs-based 6T SRAM cells investigated by 3D TCAD simulation

Munteanu, Daniéla; Autran, Jean‐Luc

doi:10.1016/j.microrel.2015.06.107

Cited by 3 publications

(3 citation statements)

References 24 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is also possible to access internal physical quantities of the numerically simulated device (such as potential, electric field, densities of carriers) at any time during the mixed-mode simulation. Furthermore, mixed-mode approaches may be used to simulate the operation of small circuits made on emerging devices (such as ultra-scaled multiple-gate or silicon nanowire-based architectures [102,103,104]) and/or to take into account new physical phenomena (e.g., quantum confinement [104] or quasi-ballistic transport) for which compact models do not exist or are still not satisfactory in terms of accuracy. In this case, all transistors contained in the small circuit can be simulated in the 3D device domain.…”

Section: Mixed-mode Tcad Applied To Seesmentioning

confidence: 99%

See 1 more Smart Citation

Multiscale, Multiphysics Modeling and Simulation of Single-Event Effects in Digital Electronics: From Particles to Systems

Autran,

Munteanu

2024

IEEE Trans. Nucl. Sci.

Self Cite

View full text Add to dashboard Cite

This review paper aims to provide a survey of modeling and simulation of single-event effects (SEEs) in digital electronics at device, circuit and system levels. It primarily focuses on the specific multi-scale, multi-physics, multi-domain nature of SEEs and on the main underlying physical mechanisms that lead to the occurrence of single events in digital devices and circuits. This review addresses the different ways to model and simulate both in space and time this complex sequence of mechanisms from the particle-material interaction up to the electrical response of a given electronics device, circuit, or system. It highlights the specific features of each methodology, and discusses simulation requirements, code or model inputs and expected outputs.

show abstract

Section: Mixed-mode Tcad Applied To Seesmentioning

confidence: 99%

“…Illustration of two mixed-mode approaches for the simulation of an SRAM cell with a single transistor (a) or the totality of the devices (b) numerically simulated in the 3D device domain and connected via a circuit netlist (the remaining transistors, in the first case, being simulated using compact models). (Adapted after Munteanu et al[102,103]). …”

mentioning

confidence: 99%

Multiscale, Multiphysics Modeling and Simulation of Single-Event Effects in Digital Electronics: From Particles to Systems

Autran,

Munteanu

2024

IEEE Trans. Nucl. Sci.

Self Cite

View full text Add to dashboard Cite

show abstract

“…The sensitivity of SRAMs to radiation has gone up with CMOS scaling [10]. Several studies on soft error performance of various JLT devices are available in the literature [11][12][13][14]. All these studies are done only in SOI based JLT devices.…”

Section: Introductionmentioning

confidence: 99%

SEU Performance Enhancement in BPJLT Devices by Channel Doping and Film Thickness

Vinodhkumar¹,

Raja²,

Addanki³

2019

IJITEE

View full text Add to dashboard Cite

The bulk planar junctionless transistor (BPJLT) is a potential candidate for future CMOS technologies due to its CMOS compatibility and scalability. In this paper, the impact of silicon film thickness and channel doping on single-event upset (SEU) radiation performance of BPJLT based SRAMs is studied using TCAD simulations. The simulation results show that BPJLT devices having higher channel doping and smaller film thickness provides the better SEU performance.

show abstract

Study on Single Event Upset and Mitigation Technique in JLTFET‐Based 6T SRAM Cell

2024

Journal of Electrical and Computer Engineering

View full text Add to dashboard Cite

The effect of single event transient (SET) on 6T SRAM cell employing a 20 nm silicon‐based junctionless tunneling field effect transistor (JLTFET) is explored for the first time. JLTFET‐based SRAM circuit is designed using the look up table‐based Verilog A code obtained from TCAD values of the device. After verifying SRAM circuit for its functionality, the stability parameters, read static noise margin (RSNM), write static noise margin (WSNM), read/write delay, and power consumption are evaluated. It is observed that the circuit has a good stability of noise margin and lesser delay. The radiation study is carried out using a transient current source striking at one of the output nodes. This causes single event upset (SEU) which changes the data stored in the memory cell giving rise to soft error (SER). SER is recovered by the radiation hardening by design (RHBD) technique with an additional RC network between two cross coupled inverters. The performance metrics, read/write delay, and the power consumption before, during, and after the radiation strike are analyzed. It is observed that SER gets totally eliminated with less recovery time at the expense of a slight increase in power and delay.

show abstract

SEU sensitivity of Junctionless Single-Gate SOI MOSFETs-based 6T SRAM cells investigated by 3D TCAD simulation

Cited by 3 publications

References 24 publications

Multiscale, Multiphysics Modeling and Simulation of Single-Event Effects in Digital Electronics: From Particles to Systems

Multiscale, Multiphysics Modeling and Simulation of Single-Event Effects in Digital Electronics: From Particles to Systems

SEU Performance Enhancement in BPJLT Devices by Channel Doping and Film Thickness

Study on Single Event Upset and Mitigation Technique in JLTFET‐Based 6T SRAM Cell

Contact Info

Product

Resources

About