SFDR considerations for current steering high-speed digital to analog converters

Abstract

In this paper the spurious free dynamic range (SFDR) of a current steering digital-to-analog converter (DAC) is related to the process parameters used for its implementation. It is shown that the realization of such DACs in advanced processes provides power and area reduction combined with faster signaling. However, it is very challenging to improve the SFDR at a certain given output swing and sampling frequency. It is demonstrated that the SFDR can be doubled by using an optimized cascode switch. It is also concluded that compared to MOSFET based approaches higher sampling frequencies can be achieved by bipolar transistor based DACs if the SFDR and transition frequency are fixed. The reason is the higher Early voltage of bipolar transistors.

A 2 GS/s 14-bit current-steering DAC in 65 nm CMOS technology for wireless transmitter

“…In a typical wireless transmitter, the base-band signals are converted to analog signals by two DACs. Current-steering architecture may be the most suitable DAC architecture because it is inherently fast and can drive resistive load without using output buffer [2]. In this work, the current source array are arranged in random switching scheme to obtain high linearity.…”

Analysis and design of high-speed digital-to-analog converters

“…Further, the layout implementation of the complex digital decoding circuit operating at highspeed is challenging as the utilization of an automatic place and route software is largely inappropriate for circuits operating at several GHz. Not unexpectedly, this architecture is typically employed for low-resolution coarse sub-DACs in segmented CS-DACs [51,52].…”

“…The segmented current-steering architectures [51,52] combine the binary and unary versions to exploit their individual advantages for a better trade-off DAC performance.…”

“…Consequently, the voltage and the parasitic capacitance at the currentsource output (drain) may vary according to the input word. These variations lead to charge variations ΔQ as expressed in Equation (2.31) [48,51].…”

“…It has been reported [29] that this phenomenon can generate a third harmonic and hence degrades the SFDR at high frequencies [24]. The relationship [29,51] between SFDR and the switching capacitor can be expressed as:…”