SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative

Nannipieri, Pietro; Bertolucci, Matteo; Baldanzi, Luca; Crocetti, Luca; Matteo, Stefano Di; Falaschi, Francesco; Fanucci, Luca; Saponara, Sergio

doi:10.1016/j.micpro.2020.103444

Cited by 23 publications

(30 citation statements)

References 6 publications

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“…Other implementation results were not available for further comparison. [30] 512 ASIC-TSMC 7nm 5100 115,200 30,740 3 -0.025 1 The accelerator is connected to the clock signal from the system bus. 2 Estimated results based on system operating frequency and number of clock cycles from [26].…”

Section: Evaluations and Discussionmentioning

confidence: 99%

“…Concerning the SHA-3 hash functions, since NIST's announcement of SHA-3, there has been a surge in research and numerous hardware implementations dedicated to this algorithm, including [28,29]. The current state-of-the-art, well-optimized ASIC implementation [30] in 7 nm TSMC also falls into this category. Evaluations between these works and our results will be discussed in Section 7.…”

Section: Related Workmentioning

confidence: 99%

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Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA

Pham

et al. 2023

Future Internet

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The security of Internet of Things (IoTs) devices in recent years has created interest in developing implementations of lightweight cryptographic algorithms for such systems. Additionally, open-source hardware and field-programable gate arrays (FPGAs) are gaining traction via newly developed tools, frameworks, and HDLs. This enables new methods of creating hardware and systems faster, more simply, and more efficiently. In this paper, the implementation of a system-on-chip (SoC) based on a 32-bit RISC-V processor with lightweight cryptographic accelerator cores in FPGA and an open-source integrating framework is presented. The system consists of a 32-bit VexRiscv processor, written in SpinalHDL, and lightweight cryptographic accelerator cores for the PRINCE block cipher, the PRESENT-80 block cipher, the ChaCha stream cipher, and the SHA3-512 hash function, written in Verilog HDL and optimized for low latency with fewer clock cycles. The primary aim of this work was to develop a customized SoC platform with a register-controlled bus suitable for integrating lightweight cryptographic cores to become compact embedded systems that require encryption functionalities. Additionally, custom firmware was developed to verify the functionality of the SoC with all integrated accelerator cores, and to evaluate the speed of cryptographic processing. The proposed system was successfully implemented in a Xilinx Nexys4 DDR FPGA development board. The resources of the system in the FPGA were low with 11,830 LUTs and 9552 FFs. The proposed system can be applicable to enhancing the security of Internet of Things systems.

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Section: Evaluations and Discussionmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA

Pham

et al. 2023

Future Internet

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“…Figure 3 shows the internal architecture of the DRBG module, which relies on a SHA2-256 core and integrates also a buffer containing the current state and a reseed counter. The output of the SHA2-256 [ 5 ] core is used to generate the output stream of the DRBG; therefore, it is constituted by random words of 256 bits, corresponding to the digest of the hashing unit. The reseed counter is in charge to signal when a new seed is required in input to the module, to refresh the entropy level of the output random stream, and to avoid it decreasing too much.…”

Section: Design Of the Random Number Generatormentioning

confidence: 99%

“…This article focuses on the design and test of an all-digital hardware accelerator for random number generation, NIST-compliant at entropy level, with sustained throughput and technology independence. The complete hardware accelerator is to be exploited within the 7 nm European Processor Initiative [ 2 ] ASIC, together with other hardware accelerators that will rely on it (AES [ 3 ], ECC [ 4 ], SHA [ 5 ]). The paper is organized as follows.…”

Section: Introductionmentioning

confidence: 99%

Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source

Crocetti

Matteo

Nannipieri

et al. 2022

Entropy

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In the cybersecurity field, the generation of random numbers is extremely important because they are employed in different applications such as the generation/derivation of cryptographic keys, nonces, and initialization vectors. The more unpredictable the random sequence, the higher its quality and the lower the probability of recovering the value of those random numbers for an adversary. Cryptographically Secure Pseudo-Random Number Generators (CSPRNGs) are random number generators (RNGs) with specific properties and whose output sequence has such a degree of randomness that it cannot be distinguished from an ideal random sequence. In this work, we designed an all-digital RNG, which includes a Deterministic Random Bit Generator (DRBG) that meets the security requirements for cryptographic applications as CSPRNG, plus an entropy source that showed high portability and a high level of entropy. The proposed design has been intensively tested against both NIST and BSI suites to assess its entropy and randomness, and it is ready to be integrated into the European Processor Initiative (EPI) chip.

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“…Architectural design of a configurable (at synthesis level) ECC crypto-processor for NIST P-256 and/or NIST P-521 elliptic curves, developed in the framework of the European Processor Initiative together with other cryptographic hardware accelerators (AES, RNG [27,28], SHA [29]). The proposed architecture supports the most used cryptographic schemes based on ECC such as ECDSA, ECDH, ECIES and ECMQV.…”

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confidence: 99%

Secure Elliptic Curve Crypto-Processor for Real-Time IoT Applications

et al. 2021

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Cybersecurity is a critical issue for Real-Time IoT applications since high performance and low latencies are required, along with security requirements to protect the large number of attack surfaces to which IoT devices are exposed. Elliptic Curve Cryptography (ECC) is largely adopted in an IoT context to provide security services such as key-exchange and digital signature. For Real-Time IoT applications, hardware acceleration for ECC-based algorithms can be mandatory to meet low-latency and low-power/energy requirements. In this paper, we propose a fast and configurable hardware accelerator for NIST P-256/-521 elliptic curves, developed in the context of the European Processor Initiative. The proposed architecture supports the most used cryptography schemes based on ECC such as Elliptic Curve Digital Signature Algorithm (ECDSA), Elliptic Curve Integrated Encryption Scheme (ECIES), Elliptic Curve Diffie-Hellman (ECDH) and Elliptic Curve Menezes-Qu-Vanstone (ECMQV). A modified version of Double-And-Add-Always algorithm for Point Multiplication has been proposed, which allows the execution of Point Addition and Doubling operations concurrently and implements countermeasures against power and timing attacks. A simulated approach to extract power traces has been used to assess the effectiveness of the proposed algorithm compared to classical algorithms for Point Multiplication. A constant-time version of the Shamir’s Trick has been adopted to speed-up the Double-Point Multiplication and modular inversion is executed using Fermat’s Little Theorem, reusing the internal modular multipliers. The accelerator has been verified on a Xilinx ZCU106 development board and synthesized on both 45 nm and 7 nm Standard-Cell technologies.

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SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative

Cited by 23 publications

References 6 publications

Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA

Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA

Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source

Secure Elliptic Curve Crypto-Processor for Real-Time IoT Applications

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