Shared-Page Management for Improving the Temporal Isolation of Memory Reservations in Resource Kernels

Kim, Hyoseung; Rajkumar, Ragunathan

doi:10.1109/rtcsa.2012.50

Cited by 10 publications

(5 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…All unrelated system services such as GUI and networking were also disabled. In addition, we used the memory reservation mechanism of Linux/RK [11,18] to protect each application against unexpected page swap-outs.…”

Section: A Experimental Setupmentioning

confidence: 99%

Bounding memory interference delay in COTS-based multi-core systems

Kim

Niz

Andersson

et al. 2014

2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)

Self Cite

179

158

View full text Add to dashboard Cite

Abstract-In commercial-off-the-shelf (COTS) multi-core systems, a task running on one core can be delayed by other tasks running simultaneously on other cores due to interference in the shared DRAM main memory. Such memory interference delay can be large and highly variable, thereby posing a significant challenge for the design of predictable real-time systems. In this paper, we present techniques to provide a tight upper bound on the worst-case memory interference in a COTS-based multi-core system. We explicitly model the major resources in the DRAM system, including banks, buses and the memory controller. By considering their timing characteristics, we analyze the worstcase memory interference delay imposed on a task by other tasks running in parallel. To the best of our knowledge, this is the first work bounding the request re-ordering effect of COTS memory controllers. Our work also enables the quantification of the extent by which memory interference can be reduced by partitioning DRAM banks. We evaluate our approach on a commodity multi-core platform running Linux/RK. Experimental results show that our approach provides an upper bound very close to our measured worst-case interference.

show abstract

Section: A Experimental Setupmentioning

confidence: 99%

Bounding memory interference delay in COTS-based multi-core systems

Kim

Niz

Andersson

et al. 2014

2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)

Self Cite

179

158

View full text Add to dashboard Cite

show abstract

“…We have implemented our scheme in Linux/RK, based on the Linux 2.6.38.8 kernel. To easily implement page coloring, we have used the memory reservation mechanism [143,144] of Linux/RK. Memory reservation maintains a global page pool to manage unallocated physical pages.…”

Section: Methodsmentioning

confidence: 99%

“…Like previous work on cache-aware response time analysis [37,39] and software cache partitioning schemes [18,19,33], we have so far assumed that tasks do not use share memory regions. However, recent operating systems widely use shared pages, not only for inter-process communication and shared libraries, but also the kernel's copy-on-write technique and file caches [144]. Suppose that two tasks share a memory region and they are allocated to different cores.…”

Section: Tasks With Shared Memory Regionsmentioning

confidence: 99%

“…For the measurement tool, we used the Linux/RK profiler [155] that records execution times and memory accesses (last-level cache misses) using hardware performance counters. In addition, we used the memory reservation mechanism of Linux/RK [143,144] to protect each application against unexpected page swap-outs. To reduce measurement inaccuracies and improve predictability, we disabled the stride-based and adjacent cacheline prefetchers, simultaneous multithreading, and dynamic clock frequency scaling of the processor.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Towards Predictable Real-Time Performance on Multi-Core Platforms

Kim¹

2016

Preprint

Self Cite

View full text Add to dashboard Cite

Cyber-physical systems (CPS) integrate sensing, computing, communication and actuation capabilities to monitor and control operations in the physical environment. A key requirement of such systems is the need to provide predictable real-time performance: the timing correctness of the system should be analyzable at design time with a quantitative metric and guaranteed at runtime with high assurance. This requirement of predictability is particularly important for safety-critical domains such as automobiles, aerospace, defense, manufacturing and medical devices.The work in this dissertation focuses on the challenges arising from the use of modern multi-core platforms in CPS. Even as of today, multi-core platforms are rarely used in safety-critical applications primarily due to the temporal interference caused by contention on various resources shared among processor cores, such as caches, memory buses, and I/O devices. Such interference is hard to predict and can significantly increase task execution time, e.g., up to 12× on commodity quad-core platforms. To address the problem of ensuring timing predictability on multi-core platforms, we develop novel analytical and systems techniques in this dissertation. Our proposed techniques theoretically bound temporal interference that tasks may suffer from when accessing shared resources. Our techniques also involve software primitives and algorithms for real-time operating systems and hypervisors, which significantly reduce the degree of the temporal interference. Specifically, we tackle the issues of cache and memory contention, locking and synchronization, interrupt handling, and access control for computational accelerators such as general-purpose graphics processing units (GPGPUs), all of which are crucial to achieving predictable real-time performance on a modern multi-core platform. Our solutions are readily applicable to commodity multi-core platforms, and can be used not only for developing new systems but also migrating existing applications from single-core to multi-core platforms. vi This dissertation would have been impossible without the help and support of many people. First and foremost, I would like to thank my advisor, Prof. Raj Rajkumar. I was lucky to work with Raj. His guidance and expertise have made me a better thinker, writer, and researcher. Raj gave me opportunities to participate in exciting projects, demonstrate my research results, and mentor other students, all of which led me to become an independent researcher and to pursue an academic career. I am grateful to the members of my thesis committee, Prof. Onur Mutlu, Prof. Anthony Rowe, and Dr. Shige Wang for their time, effort and inputs in completing this dissertation. Thanks to Onur for his insights on various aspects of my work. I learned a lot from Onur on computer architectures, which was a great asset for my research. Thanks to Anthony for his feedback and advice, even since my very early days at CMU. I enjoyed lively conversations with Anthony and liked to hear his view on cyber-physical...

show abstract

“…We have implemented our page management mechanism as part of the memory reservation scheme [8] in Linux/RK [12], which is based on the Linux 2.6.38.8 kernel. Memory reservation allows an application task to reserve a portion of the physical memory for its exclusive use.…”

Section: E Os Support For Combined Cache and Bank Coloringmentioning

confidence: 99%

Coordinated Bank and Cache Coloring for Temporal Protection of Memory Accesses

Suzuki

Kim

Niz³

et al. 2013

2013 IEEE 16th International Conference on Computational Science and Engineering

Self Cite

View full text Add to dashboard Cite

In commercial-off-the-shelf (COTS) multi-core systems, the execution times of tasks become hard to predict because of contention on shared resources in the memory hierarchy. In particular, a task running in one processor core can delay the execution of another task running in another processor core. This is due to the fact that tasks can access data in the same cache set shared among processor cores or in the same memory bank in the DRAM memory (or both). Such cache and bank interference effects have motivated the need to create isolation mechanisms for resources accessed by more than one task. One popular isolation mechanism is cache coloring that divides the cache into multiple partitions. With cache coloring, each task can be assigned exclusive cache partitions, thereby preventing cache interference from other tasks. Similarly, bank coloring allows assigning exclusive bank partitions to tasks. While cache coloring and some bank coloring mechanisms have been studied separately, interactions between the two schemes have not been studied. Specifically, while memory accesses to two different bank colors do not interfere with each other at the bank level, they may interact at the cache level. Similarly, two different cache colors avoid cache interference but may not prevent bank interference. Therefore it is necessary to coordinate cache and bank coloring approaches. In this paper, we present a coordinated cache and bank coloring scheme that is designed to prevent cache and bank interference simultaneously. We also developed color allocation algorithms for configuring a virtual memory system to support our scheme which has been implemented in the Linux kernel. In our experiments, we observed that the execution time can increase by 60% due to inter-task interference when we use only cache coloring. Our coordinated approach can reduce this figure down to 12% (an 80% reduction).

show abstract

Shared-Page Management for Improving the Temporal Isolation of Memory Reservations in Resource Kernels

Cited by 10 publications

References 14 publications

Bounding memory interference delay in COTS-based multi-core systems

Bounding memory interference delay in COTS-based multi-core systems

Towards Predictable Real-Time Performance on Multi-Core Platforms

Coordinated Bank and Cache Coloring for Temporal Protection of Memory Accesses

Contact Info

Product

Resources

About