Shortest Path Routing Algorithm for Hierarchical Interconnection Network-on-Chip

Inam, Omair; Khanjari, Sharifa Al; Vanderbauwhede, Wim

doi:10.1016/j.procs.2015.07.228

Cited by 5 publications

(2 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Authors [9] also proved that TM topology performed better than other topologies under different traffic patterns. Similar to a torus, authors in [10] discussed another topology called Hierarchical Interconnection Network-on-Chip (HCCR). It has better topological parameters than Mesh.…”

Section: Related Workmentioning

confidence: 99%

FTTCR: A New Interconnection Architecture for Parallel Systems

Tripathy

Khan²

2020

Smart Innovation, Systems and Technologies

View full text Add to dashboard Cite

Mesh and Torus are the most popular interconnection topologies. Based upon Fully Twisted Torus, a new interconnection topology is proposed and compared with some existing topologies. It is found that the proposed topology has better topological parameters than TCR, FTT, and other networks under consideration. The Fully Twisted Torus Connected Ring is an enhanced TCR interconnected network. The topological properties of the proposed network are analyzed.

show abstract

Section: Related Workmentioning

confidence: 99%

FTTCR: A New Interconnection Architecture for Parallel Systems

Tripathy

Khan²

2020

Smart Innovation, Systems and Technologies

View full text Add to dashboard Cite

show abstract

“…A new interconnection topology called the hierarchical cross connected recursive network (HCCR) and the shortest-path routing algorithm for the HCCR are proposed in Inam et al (2015). For all switching strategies, this topology improves network diameter and network connections (in buffer and edges) and reduces propagation delay in point-to-point communication.…”

Section: Introductionmentioning

confidence: 99%

Reducing the number of passing links in the 2D-NoC for performance and reliability improvement

Chabok

Alavi

2020

WJE

View full text Add to dashboard Cite

Purpose The routing algorithm is one of the most important components in designing a network-on-chip (NoC). An effective routing algorithm can cause better performance and throughput, and thus, have less latency, lower power consumption and high reliability. Considering the high scalability in networks and fault occurrence on links, the more the packet reaches the destination (i.e. to cross the number of fewer links), the less the loss of packets and information would be. Accordingly, the proposed algorithm is based on reducing the number of passed links to reach the destination. Design/methodology/approach This paper presents a high-performance NoC that increases telecommunication network reliability by passing fewer links to destination. A large NoC is divided into small districts with central routers. In such a system, routing in large routes is performed through these central routers district by district. Findings By reducing the number of links, the number of routers also decreases. As a result, the power consumption is reduced, the performance of the NoC is improved, and the probability of collision with a faulty link and network latency is decreased. Originality/value The simulation is performed using the Noxim simulator because of its ability to manage and inject faults. The proposed algorithm, XY routing, as a conventional algorithm for the NoC, was simulated in a 14 × 14 network size, as the typical network size in the recent works.

show abstract