ShuntFlow

Gong, Shangqing; Li, Jiajun; Lu, Wangtao; Yan, Guihai; Li, Xiaowei

doi:10.1145/3316781.3317910

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2019

2024

Publication Types

Select...

Article2

Book1

Other1

Relationship

Self Cite0

Independent4

Authors

Journals

Cited by 4 publications

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

Hardware Accelerators for Classification of Thoracic Disorders: A Survey

Sharma,

Gurunarayanan,

Karuppiah

2024

Proceedings of Ninth International Congress on Information and Communication Technology

View full text Add to dashboard Cite

Hardware Accelerators for Classification of Thoracic Disorders: A Survey

Sharma,

Gurunarayanan,

Karuppiah

2024

Proceedings of Ninth International Congress on Information and Communication Technology

View full text Add to dashboard Cite

Boosting general-purpose stream processing with reconfigurable hardware

Ottimo,

Mencagli,

Danelutto

2024

J Supercomput

View full text Add to dashboard Cite

Reconfigurable devices such as field-programmable gate arrays (FPGAs) offer flexible solutions to workload acceleration with high energy efficiency. Despite such a potential advantage, they often reveal hard to program by application programmers. High-level synthesis languages have been developed to provide higher-level abstractions, allowing the developers to define the FPGA behavior using an imperative programming approach based on C/C++ languages. However, such approaches still leave the developer with the responsibility to harness the low-level optimizations required to develop efficient FPGA programs. Along this line, this paper introduces , a framework helping programmers to develop FPGA-accelerated data stream processing (DSP) applications. The approach provides a high-level Python API to develop the data-flow graph of operators, which is automatically translated into an efficient Vitis source code targeting Xilinx devices. The execution of the bitstreams implementing two benchmark applications showcases the efficiency of using FPGAs for DSP workloads. In general, provides, with a reasonable time-to-solution, higher performance compared with state-of-the-art DSP frameworks.

show abstract