Si nanowire FET and its modeling

Abstract

Because of its ability to effectively suppress off-leakage current with its gate-around configuration, the Si nanowire FET is considered to be the ultimate structure for ultra-small CMOS devices to the extent that the devices would be approaching their downsized limits. Recently, several experimental studies of Si nanowire FETs with on-currents much larger than those of planar MOSFETs have been published. Consequently, Si nanowire FETs are now gaining significant attention as the most promising candidate for mainstream CMOS devices in the 2020s. To enable the introduction of the Si nanowire FETs into integrated circuits, good compact models, which circuit designers can easily handle, are essential. However, it is a very challenging task to establish such a compact model, because the I D − V D characteristics of Si nanowire FETs are affected by the band structure of the nanowire, which is very sensitive to the nanowire diameter, cross-sectional shape, crystal orientation, mechanical stress and interface states. In this paper, the recent status of research on Si nanowire FETs in experimental and theoretical studies is described.

Introduction of New Materials into CMOS Devices

“…This is called as tri-gate MOSFETs (6), and Intel has already introduced this structure into its 22 nm microprocessors. Ultimate structure is a Si nanowire FET in which Si nanowire channel is fully surrounded by the gate electrode (7)(8)(9). The fin, tri-gate, and nanowire FETs are called as multiple gate MOSFETs.…”

Systematic calibration of drift diffusion model for InGaAs MOSFETs in quasi-ballistic regime

“…To improve the accuracy of TCAD tools without lifting the time consumption, it is necessary to calibrate the DD model employed by the commercial TCAD tools using the BTE simulator. Many studies have been conducted on DD model calibration for Si devices [5][6][7] because Si is still the main stream material used in MOSFETs. Recently, III-V materials, particularly for InGaAs MOSFETs, have gained further attention [8,9] because they show high mobility and a gradually improved surface quality [10].…”

Circumventing Short Channel Effects in FETs: Review

“…Decreasing V DD may have multiple repercussions such as scaling the threshold voltage V th which in turn increases the leakage current and static power in the sub-threshold regime. Use of Tunnel Field Effect Transistor (TFETS) is advantageous over a traditional MOSFET fabricated in a bulk silicon wafer as the subthreshold slope should not be less than 60mV per decade limit [15]- [18]. Short Channel Effects (SCE) may be attributed to the DIBL effect which reduces the threshold voltage as the channel length is scaled.…”