SIC-TPG for path delay fault detection in VLSI circuits using scan insertion method

Hussain, Sabir; Raheem, Mohammed Abdul; Ahmed, Afaq

doi:10.1109/devic50843.2021.9455859

Cited by 3 publications

(1 citation statement)

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“…In our experiment we use a low power consumed LFSR, which uses bit-swapping technique to reduce the power in test mode [8]. As shown in Figure 4, an LFSR consists of two parts; A Shift Register (SR) and a feedback function.…”

Section: B Built-in Self-testmentioning

confidence: 99%

ASIC vs FPGA based Implementations of Built-In Self-Test

Ahmad¹,

Hussain²,

Raheem³

et al. 2023

IJANSER

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Linear Feedback Shift Registers (LFSRs) are play key role in testing of for Very Large Scale Integration (VLSI) Integrated Circuits (ICs) testing. Due to tremendous IC complex growth, testing of recent VLSI ICs technology have become more complicated. This led to develop a popular alternate viable solution in the form of Built-In Self-Test (BIST) technology as compared to Automatic Test Equipment (ATE). However, the challenges of BIST technology remain the subject of research. Furthermore, implementation of BIST’s LFSR on Application Specific Integrated Circuit (ASIC) versus Field Programmable Gate Array on (FPGA) platform is current area of research especially in context to power consumption. Hence, to make an informed choice between ASIC and FPGA for implementing BIST’s LFSR we focus on study of design of reconfigurable LFSR on ASIC versus FPGA platform. The Electronic Design Automation (EDA) tool, Cadence is used for implementing BIST’s LFSR on ASIC platform. Whereas, Hardware Description Language (HDL), Verilog is used to implement BIST’s LFSR on FPGA platform. During experimental methodology, maximum frequency, the critical path delay is investigated to assess the power dissipation. The functional and timing simulation models are used to verify the implemented reconfigurable BIST’s LFSR designs. The obtained results show that the performance, in terms of speed and power, of ASIC implementation is far better than traditional FPGA implementation.

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Section: B Built-in Self-testmentioning

confidence: 99%