Side-channel attack resilience through route randomisation in secure real-time Networks-on-Chip

Abstract

Abstract-Security can be seen as an optimisation objective in NoC resource management, and as such poses trade-offs against other objectives such as real-time schedulability. In this paper, we show how to increase NoC resilience against a concrete type of security attack, named side-channel attack, which exploit the correlation between specific non-functional properties (such as packet latencies and routes, in the case of NoCs) to infer the functional behaviour of secure applications. For instance, the transmission of a packet over a given link of the NoC may hint on a cache miss, which can be used by an attacker to guess specific parts of a secret cryptographic key, effectively weakening it.We therefore propose packet route randomisation as a mechanism to increase NoC resilience against side-channel attacks, focusing specifically on the potential impact of such an approach upon hard real-time systems, where schedulability is a vital design requirement. Using an evolutionary optimisation approach, we show how to effectively apply route randomisation in such a way that it can increase NoC security while controlling its impact on hard real-time performance guarantees. Extensive experimental evidence based on analytical and simulation models supports our findings.

Side-channel protected MPSoC through secure real-time networks-on-chip

“…In this paper, we concentrate on a threat model based on packet timing. This paper extends our earlier conference paper work upon security through routing randomisation in NoCs [9]. In summary, the contributions of our total work upon this idea are:…”

“…IoT context due to the interaction between secure and malicious downloaded code communicating over a shared NoC. A novel case study involving an autonomous vehicle is added in this paper, over that presented in [9].…”

“…• Present an experiment performed on a NoC hardware platform in order to motivate route randomisation as a viable approach for improving security -the current publication adds this upon the earlier work in [9] • Define a schedulability analysis for determining the worst-case end-toend latency in the case of randomised routing…”

A Survey on the Security of Wired, Wireless, and 3D Network-on-Chips

“…These countermeasures can profoundly enhance data confidentiality, while they might not be able to address DoS attacks such as packet misrouting, packet dropping, and packet tampering. Routers are literally the first line of defense, so researchers have also used routers to integrate their security solutions [32], [35], [36], [51], [52]. Suppose a packet injected by a malicious task is heading towards a secured zone of the network to carry out an attack, e.g., timing attack, spoofing attack, etc.…”

On a New Hardware Trojan Attack on Power Budgeting of Many Core Systems

“…DoS attacks on a many-core chip can target different components of the chip, including the memory system [15], and the network-on-chip (NoC) [16], [17]. With the help of hardware Trojans (HTs) [3], [4], [13], DoS attacks can be classified as 1) flooding attack [18], [19], where a large volume of useless packets floods a victim node and saturates it; 2) packet drop attack, where some packets are dropped or directed to some malicious nodes so that the victim node can never receive a single packet designated to it [20]; 3) privilege escalation attack [21], where an average user process is granted the privileges of a supervisor so that it can steal passwords; and 4) routing loop attack [2], where packets that pass the malicious node will be routed back to the source node, effectively blocking the source core from communicating with any other cores.…”