Signal Integrity Analysis for Dual-Stripline Design

Huang, Nick K. H.; Tseng, Bin-Chyi

doi:10.1109/edaps47854.2019.9011618

Cited by 3 publications

(2 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, this can also lead to severe near-end crosstalk (NEXT) and farend crosstalk (FEXT) issues due to the absence of ground shielding between adjacent signal layers. These crosstalk issues in dual-stripline routing have been studied before and some mitigation techniques have also been proposed in [2]- [5]. One method discussed in [2] is to reduce the NEXT and FEXT effects by employing new routing strategies that vary the inter-pair spacing.…”

mentioning

confidence: 99%

“…However, these studies primarily concentrate on analyzing the dual-stripline structure in PCB board-level designs, particularly targeting low-density interconnects. Other studies, such as those mentioned in [4] and [5], explore novel routing strategies involving twisted pairs or angular bends to mitigate crosstalk problems. Nonetheless, these techniques require more space and result in lowerdensity interconnects.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Dual-Stripline Configuration for Efficient Routing in Chiplet Interconnects

Geedimatla,

Balachandran,

Vysakham

et al. 2024

Preprint

View full text Add to dashboard Cite

Routing density is becoming in big challenge in die-to-die interconnects. In this paper, we propose use of the dual-stripline configuration for routing signals in high-density interconnects. The scheme can improve the routing density by up to 33% when compared with the conventionally used stripline configuration. To address the challenges of crosstalk due to the proximity between vertically adjacent signal lines, halfpitch offset between lines on vertically adjacent layers has been proposed. The proposed routing scheme has been validated using 3D full-wave electromagnetic simulations. The simulations show that the scheme can be used for increasing the routing density in the Bunch-of-wires interface by 25%, while meeting all the Bunch-of-wires channel specifications, which include eye-opening value above 60% unit interval at a bit error rate of 10, with data rates of 16 Gbps per wire.

show abstract

mentioning

confidence: 99%

mentioning

confidence: 99%